Provided are devices, methods, systems, computer readable storage media and other means for tokenizing data. In some examples, credit card numbers are tokenized using a pre-generated token map and absent the use of a networked database that stores a relatively large quantity of credit card numbers in a central location. The token map may be generated by a token map generator such that the token map can be used by a tokenizer to replace a portion of an account number with a token, and by a detokenizer to replace the token with the original portion of the account number. A pre-parser and parser may also be used to locate an account number and/or token in a message received over a network.

Tokenized data security

A language for semi-structured documents, XML has emerged as the core of the Web services architecture, and is playing crucial roles in messaging systems, databases, and document processing However, the processing of XML documents has a reputation for poor performance, and a number of optimizations have been developed to address this performance problem from different perspectives, none of which have been entirely satisfactory In this paper, we present a seemingly quixotic, but novel approach: parallel XML parsing Parallel XML parsing leverages the growing prevalence of multicore architectures in all sectors of the computer market, and yields significant performance improvements This paper presents our design and implementation of parallel XML parsing Our design consists of an initial preparsing phase to determine the structure of the XML document, followed by a full, parallel parse The results of the preparsing phase are used to help partition the XML document for data parallel processing Our parallel parsing phase is a modification of the libxml2 in Veillard, D (2004) XML parser, which shows that our approach applies to real-world, production quality parsers Our empirical study shows our parallel XML parsing algorithm can improved the XML parsing performance significantly and scales well

A Parallel Approach to XML Parsing

A remote direct memory access (RDMA) system is provided in which data is transferred over a network by DMA between from a memory of a first node of a multi-processor system having a plurality of nodes connected by a network and a memory of a second node of the multi-processor system. The system includes a first network adapter at the first node, operable to transmit data stored in the memory of the first node to a second node in a plurality of portions in fulfillment of a DMA request. The first network adapter is operable to transmit each portion together with identifying information and information identifying a location for storing the transmitted portion in the memory of the second node, such that each portion is capable of being received independently by the second node according to the identifying information. Each portion is further capable of being stored in the memory of the second node at the location identified by the location identifying information.

Remote direct memory access system and method

Aspects of the invention may comprise receiving an incoming TCP packet at a TEEC (270) and processing at least a portion of the incoming packet once by the TEEC (270) without having to do any reassembly and/or retransmission by the TEEC (270). At least a portion of the incoming TCP packet may be buffered in at least one internal elastic buffer (280,290) of the TEEC (270). The internal elastic buffer (280,290) may comprise a receive internal elastic buffer (290) and/or a transmit internal elastic buffer (280). Accordingly, at least a portion of the incoming TCP packet may be buffered in the receive internal elastic buffer (290). At least a portion of the processed incoming packet may be placed in a portion of a host memory (230) for processing by a host processor or CPU (210). Furthermore, at least a portion of the processed incoming TCP packet may be DMA transferred to a portion of the host memory (230).

System and method for TCP offload

Systems and methods for network interfacing may include a communication data center with a first tier, a second tier and a third tier. The first tier may include a first server with a first single integrated convergent network controller chip. The second server may include a second server with a second single integrated convergent network controller chip. The third tier may include a third server with a third single integrated convergent network controller chip. The second server may be coupled to the first server via a single fabric with a single connector. The third server may be coupled to the second server via the single fabric with the single connector. The respective first, second and third server, each processes a plurality of different traffic types concurrently via the respective first, second and third single integrated convergent network chip over the single fabric that is coupled to the single connector.

System and method for network interfacing

An apparatus and method for managing the receipt of communication traffic in the form of packets or other units. The apparatus includes a communication interface (e.g., a NIC, a TCA) coupled to one or more host computer systems. Through Direct Memory Access (DMA) operations, the interface reassembles payloads of received packets in host buffers based on their sequence numbers, without buffering them in the interface. Packet headers are separated from the payloads and passed to a host for protocol processing after the payload DMA is completed. Host buffers may be of virtually any size. For each communication connection, state information is maintained on the interface, which may identify an upper level protocol so that an upper level protocol header is passed to the host as part of the packet header, not as part of the payload. Protocol termination remains in the host.

Method and apparatus for zero-copy receive buffer management

A hardware unit for parsing an XML document includes embedded logic or circuitry for accessing the document, decoding it to change a character set, validating individual characters of the document, extracting tokens, maintaining a symbol table and generating binary token headers to describe the document's structure and convey the document's data to an application. Tokenization, the process of identifying tokens and generating token headers, may be controlled by a finite state machine that recognizes XML delimiters in the document's markup and activates state transitions based on the current state and the recognized delimiter. The parser unit may be implemented within a hardware XML accelerator that includes a processor, a DMA engine, a cryptographic engine, memory (e.g., for storing a document, maintaining a symbol table) and various interfaces (e.g., network, memory, bus).

Hardware unit for parsing an xml document

A method and apparatus for accelerating processing of a structured document A hardware XML accelerator includes one or more processors (eg, CMT processors), one or more hardware XML parser units, one or more cryptographic units and various interfaces (eg, to memory, a network, a communication bus) An XML document may be processed in its entirety or may be parsed in segments (eg, as it is received) A parser unit parses a document or segment character by character, validates characters, assembles tokens from the document, extracts data, generates token headers (to describe tokens and data) and forwards the token headers and data for consumption by an application A cryptographic unit may enforce web security, XML security or some other security scheme, by providing encryption/decryption functionality, computing digital signatures, etc Software processing, bus utilization and latencies (eg, memory, bus) are greatly reduced, thereby providing significantly improved XML processing and security processing throughput

Method and apparatus for hardware xml acceleration

A method and apparatus for performing virtualized parsing of an XML document. A document is divided into multiple segments, which may correspond to disk blocks, memory pages, separate packets containing portions of the document, etc. For each segment, a processor operating within an XML accelerator initiates parsing by identifying to a hardware parsing unit the document segment, a symbol table for the document and a location for storing state information regarding the parsing. Each segment is parsed in sequence, and the state information of the parsing is stored after each segment is completed, for retrieval when the next segment is to be parsed.

Method and apparatus for virtualized xml parsing

A hardware finite state machine for facilitating the processing of an XML (Extensible Markup Language) document or other structured data stream. An accelerator is implemented in hardware to enable fast processing of a document (or a segment thereof). The accelerator includes a finite state machine that embodies a ternary CAM (Content-Addressable Memory) and associated RAM (Random Access Memory). Processing of the document is divided into multiple states, with each state transition defined by a markup delimiter that triggers the transition. The CAM is programmed with entries containing the processing states and, for each possible transition from that state, a pattern for matching delimiters that trigger the possible transitions. For a CAM entry matching the current processing state and a sequence of characters from the document, which may contain a delimiter, the associated RAM identifies the next state and any action to be taken (e.g., to shift the sequence of characters).

Programmable hardware finite state machine for facilitating tokenization of an XML document

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