High observability testing environment allows internal circuit nodes to be used as test points. However, such flexibility requires the development of new ATPG algorithm. Previous reported algorithm does not guarantee full fault-coverage and assumes all internal circuit nodes are test points. The new algorithm described in this paper will generate a full fault-coverage test set for a fanout free combinational circuit. The main characteristic of the algorithm is that it generates test vectors as well as probe points. As a result, the probe points are different for each test vector, and the number of probe points is the minimum for test set generated. Results obtained show that an average of 30% test vector reduction is achieved compared with the conventional test method which uses only output pins as test points.

Test generation with dynamic probe points in high observability testing environment

The use of library cells, specially designed for their sensitivity to a laser beam, is a potential solution for both ‘observability’ and ‘controllability’ problems encountered by the test engineers. The basic principle relies on the photo-induced current generated in the laser beam-silicon interaction. The ‘observation’ cells, when probed by the beam, are used to read directly a logic level inside the circuit, whereas the ‘control’ cells are used to force a particular node of the circuit. A test structure including a 16 bits counter with 16 ‘observation’ cells and 1 ‘control’ cell has been fabricated in BiCMOS technology in order to illustrate this new testing method.

Implementation of Laser Beam Sensitive Cells : a new approach for integrated circuits testing

Testability improvements using e-beam controllability: principle and design for electron-beam testability

With the increasing use of E-beam testing, chip test under highly observable condition has become increasing important. Using E-beam probing, the logical value of the internal signal lines running in the top-metal layer can be observed directly. The number of test vectors can be reduced by observing internal nodes. In this paper, we access a method to generate test vectors and corresponding internal nodes for single stuck-at faults in combinational circuits. This approach differs from the conventional methods which generates test vectors with a fixed number of observable points. >

Test generation for E-beam testing of VLSI circuits

Bridging the gap between conventional and E-beam testing

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Bridging the gap between conventional and E-beam testing