Self-timed circuits appear today as an attractive solution for designing robust and low-power chips dedicated to smart sensing and Internet of Things (IoT) platforms. However, a massive adoption of this technology by the industry requires industrial-grade tools for the whole design flow. The gap between asynchronous bundled-data and synchronous circuits is sufficiently tight to exploit the existing commercial tools without impacting the design flow and the time-to-market. This paper especially addresses the timing analysis of asynchronous bundled-data circuits with standard EDA tools and presents a method for exhaustively defining and verifying their relative timing constraints. This new approach only uses a combination of clocks to describe every possible event propagation path, allowing the tools to fully capture the relative timing constraints. Moreover, this can be adapted to different controller implementations and fully automated. A case-study, based on a 128-bit AES implemented in UMC 55nm uLP technology, illustrates the proposed methodology and evaluates its efficiency in terms of complexity and execution time.

Static Timing Analysis of Asynchronous Bundled-Data Circuits

In this paper, an in-depth timing analysis of asynchronous bundled-data circuits is presented. We leverage the controller Signal Transition Graph to extract and classify their relative timing constraints. Thanks to the Local Clock Set methodology, we show how to define generic rules to translate these constraints into SDC commands for standard EDA tools. As examples, three 2-phase protocols and four 4-phase protocols are analyzed, covering both flip-flop-based and latch-based designs. Additionally, this methodology has been applied to define the timing constraints of reactive clock circuits. Moreover, the method is beneficial for comparing the different bundled-data circuit implementations in terms of timing constraints complexity and timing analysis execution time.

From Signal Transition Graphs to Timing Closure: Application to Bundled-Data Circuits

Stateful Timed CSP has been recently proposed to model (and verify) hierarchical real-time systems. It is an expressive modeling language which combines data structure/operations, complicated control flows (modeled using compositional process operators adopted from Timed CSP), and real-time requirements like deadline and within. It has been shown that Stateful Timed CSP is equivalent to closed timed automata with silent transitions, which implies that the timing constraints of Stateful Timed CSP can be captured using explicit tick events, through digitization. In order to tackle the state space explosion problem, we develop a BDD-based symbolic model checking approach to verify Stateful Timed CSP models. Due to the rich language features, BDD-based system encoding and verification is highly nontrivial. In this work, we show how to systematically encode Stateful Timed CSP models in BDD. Our approach consists of two steps. The first step is to identify maximum primitive components of a given system and then generate finite state machines (FSMs) from them, applying a set of symbolic firing rules. These FSMs are then encoded in the standard way. The second step is to compose the encoded components using a set of BDD-based compositional functions. The proposed method has been implemented in the PAT model checker. It supports properties like reachability, linear temporal logic, etc. The effectiveness of our technique is evaluated with benchmark systems.

/pdf/symbolic-model-checking-of-stateful-timed-csp-using-bdd-and-1ckcvmwyu6.pdf

Symbolic model-checking of stateful timed CSP using BDD and digitization

Accurate delay modeling beyond static models is critical to garnering better correlation with post-silicon analysis. Furthermore, post-silicon timing validation requires a pattern-dependent timing model to generate patterns. To address these issues, a timing analysis tool was proposed that integrates a data-dependent delay model into its analysis. The approach solves for the delay by using the concept of circuit unrolling and formulation of timing questions as decision problems for input into a SAT solver. The effectiveness and validity of the proposed methodology is illustrated through experiments on benchmark circuits

/pdf/accurate-timing-analysis-using-sat-and-pattern-dependent-2tuilvwgxx.pdf

Accurate timing analysis using SAT and pattern-dependent delay models

This thesis considers the area of constraint programming, more specifically, knowledge compilation for the use in decision support. In particular decision support for configuration problems is considered. The main contributions of the thesis are the following: Decision support on unbounded string domains A technique is presented that offers decision support for CSPs that contain variables on unbounded string domains and constraints with regular language membership tests on the string variables. The technique has been implemented and it is empirically shown that the technique can support a real-time response on real-world instances. Comparing decision diagrams We compare acyclic DFAs and MDDs and conclude that the difference between the two in structure as well as in size is negligible. We compare direct-encoded BDDs with log-encoded BDDs and empirically show that a direct encoded BDD is orders of magnitudes larger than a corresponding log-encoded BDD. Further the use of ZBDDs for compiling CSPs is proposed and it is empirically shown that on tight instances, ZBDDs result in smaller representations than BDDs for both log-encoded and direct encoded decision diagrams. Succinct representation of decision diagrams We present a succinct representation of a BDD based on the reuse of shared substructures and a succinct representation of an MDD based on merging edges that share labels and endpoints. Both representations supports traversal, restriction and computation of generalized arc consistency. Further a technique for BDD compression is proposed, for the case where no queries on the compressed decision diagram have to be supported. All three succinct representations are empirically tested on real-world instances.

Decision Support using Finite Automata and Decision Diagrams

Symbolic model checking of timed guarded commands using difference decision diagrams

We describe a methodology for analyzing timed systems symbolically. Given a formula representing a set of timed states, we describe howto determine a new formula that represents the set of states reachable by taking a discrete transition or by advancing time. The symbolic representations are given as formulae expressed in a simple first-order logic over constraints of the form x-y ? d which can be combined with Boolean operators and existentially quantified. The main contribution is a way of advancing time symbolically essentially by quantifying out a special variable z which is used to represent the current zero point in time. We describe how to model asynchronous circuits using timed guarded commands and provide examples that demonstrate the potential of the symbolic analysis.

Timed Verification of Asynchronous Circuits

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Symbolic model checking of timed guarded commands using difference decision diagrams

Timed Verification of Asynchronous Circuits