An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.

Semiconductor device, and manufacturing method thereof

A control system and method for simultaneously regulating the operation of a plurality of different types of switching power converters. The system utilizes in regulating the power converters sampled data and nonlinear feedback control loops.

Power converter circuitry and method

There is provided a semiconductor package and method for fabricating the same. An embodiment of the semiconductor package includes: a semiconductor chip having a first face and a second face, the first face having a plurality of input/output pads formed thereon; a circuit board composed of a resin film having a first face and a second face, a circuit pattern layer including a plurality of bond fingers and ball lands, and a cover coat covering the circuit pattern layer and selectively exposing the plurality of bond fingers and ball lands, the circuit pattern layer being formed on the first face of the resin film, the circuit board having a through hole at the center thereof, the semiconductor chip being placed in the through hole; electrical connection means for electrically connecting the input/output pads of the semiconductor chip to the bond fingers of the circuit board; an encapsulant for encapsulating the semiconductor chip, connection means and a part of the circuit board; and a plurality of conductive balls fused to the circuit board. Accordingly, the semiconductor package becomes very thin and its heat spreading performance is improved.

Semiconductor package and method for fabricating the same

An object is to provide a method for manufacturing a semiconductor device, in which the number of photolithography steps can be reduced, the manufacturing process can be simplified, and manufacturing can be performed with high yield at low cost A method for manufacturing a semiconductor device includes the following steps: forming a semiconductor film; irradiating a laser beam by passing the laser beam through a photomask including a shield for shielding the laser beam; subliming a region which has been irradiated with the laser beam through a region in which the shield is not formed in the photomask in the semiconductor film; forming an island-shaped semiconductor film in such a way that a region which is not irradiated with the laser beam is not sublimed because it is a region in which the shield is formed in the photomask; forming a first electrode which is one of a source electrode and a drain electrode and a second electrode which is the other one of the source electrode and the drain electrode; forming a gate insulating film; and forming a gate electrode over the gate insulating film

Method for Manufacturing Semiconductor Device

A configurable logic array may include: a multiplicity of logic cells, containing look-up tables; customizable metal and via connection layers overlaying the multiplicity of logic cells; a multiplicity of device customizable I/O cells; a multiplicity of configuration customizable RAM blocks; a ROM block with customizable contents; and a microprocessor with customizable I/O for configuring and testing the array, where the customizations are all done on a single via layer.

Structured integrated circuit device

A dynamic random access memory solves long-existing tight pitch layout problems using a multiple-dimensional bit line structure. Improvement in decoder design further reduces total area of this memory. A novel memory access procedure provides the capability to make internal memory refresh completely invisible to external users. By use of such memory architecture, higher performance DRAM can be realized without degrading memory density. The requirements for system support are also simplified significantly.

High performance embedded semiconductor memory devices with multiple dimension first-level bit lines

The present invention discloses novel methods to transfer data between a plurality of integrated circuit dice on a semiconductor wafer. Each individual die contains internal circuits to control data transfer to nearby dice. Wafer level data transfer is achieved by a series of inter-dice data transfers. It is therefore possible to use a small number of small area metal lines to support wafer level parallel processing activities. External connections are provided by a small number of bonding pads on each wafer. The load on each external bounding pad is by far lower than that of prior art wafer level connections. These inter-dice data transfer mechanism also can be programmed to avoid defective circuitry. This invention has been used to support wafer level functional tests and wafer level burn-in tests. A Testing system of the present invention can test thousands of dice in parallel using simple testing equipment. Testing costs for integrated circuits are therefore reduced dramatically. The present application also makes it possible to build large area IC containing multiple dice. Extremely powerful products are realized using parallel processing capability of such multiple die integrated circuits.

Inter-dice wafer level signal transfer methods for integrated circuits

This invention provides practical methods to fabricate sub-micron 3D integrated circuits using multiple layers of diodes manufactured on polycrystalline or amorphous semiconductor thin films. The long existing problems for using poly diodes for high density IC are solved by design and manufacture methods. The circuit design methods of the present invention improve the tolerance in non-ideal properties of diodes. The resulting IC products can function correctly even when many of their diodes are defective. We also developed manufacture procedures fully compatible with current art IC technologies. No additional masking steps or high temperature procedures are used. The 3D IC devices of the present invention are ready to be manufactured by current art IC technologies. Integrated circuits with unprecedented densities are therefore realized by stacking thin film diodes upon common active devices.

Three dimensional integrated circuits using sub-micron thin-film diodes

A semiconductor memory array comprises a plurality of memory cells wherein each memory cell further includes a first and a second bit-lines and a first and a second word-lines connected to each of the memory cells. The memory array further includes a memory cell read/write voltage control circuit for controlling each of the first and second bit-lines to have a bitline voltage higher, lower and within a medium voltage range between a first voltage V 0 and second voltage V 1 wherein Vdd>V 1 >V 0 >Vgnd where Vdd is a power supply voltage, and Vgnd is a ground voltage for the memory array. The memory array further includes a first read/write port and a second read/write port for independently carrying out a read/write operation by activating the first and second word-lines respectively and by controlling the first and second bit-lines respectively to have a bit-line voltage higher, lower or within the medium voltage range between the first and the second voltage. In a preferred embodiment, the memory cell read/write voltage control circuit further includes a wordline voltage control circuit for providing a higher wordline voltage in a write operation and a lower wordline voltage in a read operation. In another preferred embodiment, the memory cell read/write voltage control circuit further includes a memory-core power supply voltage (CVdd) control circuit for providing a higher CVdd voltage in a read operation and a lower CVdd voltage in a write operation. In another preferred embodiment, the memory cell read/write voltage control circuit further includes a memory-core ground voltage (CVss) control circuit for providing a lower CVss voltage in a read operation and a higher CVss voltage in a write operation.

Multiple ports memory-cell structure

Long existing performance, noise, and power consumption problems of prior art output drivers are solved by using n-channel transistors as pull up transistors and p-channel transistors as pull down transistors for high performance output drivers. Output drivers of the present invention can be fully compatible with HSTL or SSTL interfaces without using termination resistors. High resolution switching applications are also made possible without consuming much power. Output drivers of the present invention provide excellent solutions to support high performance interface while consuming much lower power.

High performance low power multiple-level-switching output drivers

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