Indranil Chatterjee
University of Bristol
41 Papers
199 Citations
Indranil Chatterjee is an academic researcher from University of Bristol. The author has contributed to research in topics: Soft error & Leakage (electronics). The author has an hindex of 14, co-authored 41 publications. Previous affiliations of Indranil Chatterjee include Vanderbilt University & Airbus Defence and Space.
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Papers
“Leaky Dielectric” Model for the Suppression of Dynamic $R_{\mathrm{ON}}$ in Carbon-Doped AlGaN/GaN HEMTs
Michael J. Uren,Serge Karboyan,Indranil Chatterjee,Alexander Pooth,Peter Moens,Abhishek Banerjee,Martin Kuball +6 more
TL;DR: In this article, the authors identify the causes of dynamic dispersion using substrate bias ramps to isolate the leakage paths and trapping locations in the epitaxy and simulation to identify their impact on the device characteristics.
Impact of Technology Scaling on SRAM Soft Error Rates
Indranil Chatterjee,Balaji Narasimham,N. N. Mahatme,N. N. Mahatme,Bharat L. Bhuva,Robert A. Reed,Ronald D. Schrimpf,J. K. Wang,Narayana Rao Vedula,B. Bartz,Carl Monzel +10 more
TL;DR: In this paper, the authors compared the heavy-ion induced upset cross-section in 28, 40, and 65 nm dual-well and triple-well SRAMs over a wide range of particle LETs.
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Bias Dependence of Single-Event Upsets in 16 nm FinFET D-Flip-Flops
Balaji Narasimham,Safar Hatami,Ali Anvar,David Harris,Alvin Lai Lin,J. K. Wang,Indranil Chatterjee,Kai Ni,Bharat L. Bhuva,Ronald D. Schrimpf,Robert A. Reed,Michael W. McCurdy +11 more
TL;DR: In this paper, the SEU cross section of FinFET-based D-flip-flops was measured with alpha particles, protons, neutrons, and heavy-ions.
Single-Event Charge Collection and Upset in 40-nm Dual- and Triple-Well Bulk CMOS SRAMs
Indranil Chatterjee,Balaji Narasimham,N. N. Mahatme,Bharat L. Bhuva,Ronald D. Schrimpf,J. K. Wang,B. Bartz,E. Pitta,M. Buer +8 more
TL;DR: In this paper, a comparative analysis of heavy ion-induced upsets in dual-well and triple-well 40-nm CMOS SRAMs is presented, showing that triplewell technologies are more vulnerable to low-LET particles, while dualwell technologies were more sensitive to highLET particles.
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Analysis of soft error rates in combinational and sequential logic and implications of hardening for advanced technologies
N. N. Mahatme,Indranil Chatterjee,Bharat L. Bhuva,J. R. Ahlbin,Lloyd W. Massengill,R.L. Shuler +5 more
- 02 May 2010
TL;DR: A model that explains the soft error rates as a function of frequency is developed to account for the inconsistency in observed data and implications for hardening against soft errors for advanced technologies are discussed.
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