Systems and methods for providing accelerated data storage and retrieval utilizing lossless data compression and decompression. A data storage accelerator includes one or a plurality of high speed data compression encoders that are configured to simultaneously or sequentially losslessly compress data at a rate equivalent to or faster than the transmission rate of an input data stream. The compressed data is subsequently stored in a target memory or other storage device whose input data storage bandwidth is lower than the original input data stream bandwidth. Similarly, a data retrieval accelerator includes one or a plurality of high speed data decompression decoders that are configured to simultaneously or sequentially losslessly decompress data at a rate equivalent to or faster than the input data stream from the target memory or storage device. The decompressed data is then output at rate data that is greater than the output rate from the target memory or data storage device. The data storage and retrieval accelerator method and system may employed: in a disk storage adapter to reduce the time required to store and retrieve data from computer to disk; in conjunction with random access memory to reduce the time required to store and retrieve data from random access memory; in a display controller to reduce the time required to send display data to the display controller or processor; and/or in an input/output controller to reduce the time required to store, retrieve, or transmit data.

System and methods for accelerated data storage and retrieval

Digital systems based on programmable logic devices and systems on chip often use register buffers for the transmission of signals between functional units. In this paper, structural models of finite state machines (FSMs) that allow the use of input and output buffer triggers as memory elements of the finite state machine are considered. To this end, a new classification of structural models of finite state machines is proposed in which all finite state machines are divided into six classes A, B, C, D, E, and F. In the models C and D, output buffer triggers are used as memory elements; in the models E and F, input buffer triggers are used for this purpose. A definition of the set of internal states of FSMs in each class is given and synthesis methods for the FSMs of the classes C-F are proposed. The results of experiments showed that the use of FSM models of the classes C-F reduces the number of internal memory elements by 2.22% to 25.83% on the average and sometimes even by 100%.

Structural models of finite-state machines for their implementation on programmable logic devices and systems on chip

Binary decision automata are finite state machines that evaluate switching functions by means of decision rather than Boolean logic. The capability of binary decision machines (BDMs) to evaluate sequential functions is addressed by the authors. The BDM is shown to be less powerful than the deterministic finite automation (DFA) model from automata theory. However, an extended BDM with input control is shown to be equivalent to the DFA and thus can be used to implement finitely computable sequential functions. The use of a BDM finite automaton instead of a more general model is motivated on the basis of expected case time and space complexity analysis. A hardware design following from this analysis is described, and programming methods are discussed. >

Advances in binary decision based programmable controllers

Systems and methods for providing accelerated transmission of broadcast data, such as financial data and news feeds, over a communication channel using data compression and decompression to provide secure transmission and transparent multiplication of communication bandwidth, as well as reduce the latency associated with data transmission of conventional systems.

Systems and methods for data block decompression

A microsequencer presented in the paper features branching on values of a subset of up to m binary variables selected arbitrarily out of the complete set of n input variables, m

Microseqencer architecture supporting arbitrary branching up to 2m targets

A general model of a memory-based finite-state machine architecture is introduced, the 2k− decision machine (2k− D). The classical (2n− D) and binary decision (2 − D) architectures are shown to be special cases of the 2k− D architecture. The equivalence among the 2k− D solutions for different values of k follows from the sequentialization principle, which is stated in the paper. A cost measure is defined in terms of memory size and a procedure to determine the 2k− D architecture which offers the minimum cost, given that the speed is equal to one state transition per clock cycle, is presented. It is shown that this architecture is not in general the minimum cost solution when the speed of the circuit is not a critical design factor. Also discussed, are the optimization problems to be solved when a minimum cost 2k− D architecture is desired. In addition, bounds on the cost of the 2k− D architecture are calculated in terms of simple measures taken from the mathematical model describing the behavior of the state machine. The results of this research are particularly attractive when LSI and VLSI technologies are considered. State machines constitute fundamental blocks in systems to be fabricated as integrated circuits. Memory-based implementations offer a short design time, regularity of structure, and expandability.

A General Model for Memory-Based Finite-State Machines

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A General Model for Memory-Based Finite-State Machines