The invention discloses a high-speed data collection system for a radio telescope, which is characterized in that, a high-performance analog-to-digital conversion module is combined with a high-speed Ethernet transmission module to realize high-speed data collection and transmission requirements of the radio telescope, and spectrum processing can be carried out on the data in real time The high-speed data collection system comprises an analog front-end unit used for receiving a weak effective signal collected by the telescope and converting the weak effective signal into an intermediate frequency signal with a high signal to noise ratio; an analog-to-digital A/D conversion unit used for receiving the intermediate frequency signal and converting the intermediate frequency analog signal into a digital signal; an FPGA control processing unit used for preprocessing the digital signal to form a frequency domain signal after digital power detection; and a data transmission unit used for outputting final data to an external server through a 10G Ethernet at a high speed The high-speed data collection system disclosed by the invention is used for establishing a high-speed astronomical data collection platform, which can meet the requirements of high-speed, high-quality, stable and reliable collection of radio astronomical data

High-speed data collection system for radio telescope

The invention discloses a land-to-air wideband communication system for an unmanned aerial vehicle. The system comprises an emission end for the unmanned aerial vehicle and a receiving end for ground equipment. The emission end comprises a first FPGA, a DAC, a filtering circuit and a radio-frequency emission module. The receiving end comprises a radio-frequency receiving module, a medium-frequency filtering module, an ADC and a second FPGA. The radio-frequency receiving module receives communication signals from the outside and control signals from the second FPGA. The output of the radio-frequency receiving module is connected with the medium-frequency filtering module. The output of the medium-frequency filtering module is connected with the second FPGA through the ADC. The gain control output of the second FPGA is connected with the radio-frequency receiving module. The second FPGA outputs demodulation data through an inner interface. A land-to-air communication subsystem which can carry out telemetering, remote control and data transmission in the system of the unmanned aerial vehicle is improved, and the system has the advantages of being low in emission end power loss, accurate in receiving end data processing and the like.

Land-to-air wideband communication method for unmanned aerial vehicle

The invention discloses a receiving terminal and method for a ground-air broadband communication system for an unmanned aerial vehicle. The receiving terminal for the ground-air broadband communication system for the unmanned aerial vehicle comprises a radio frequency receiving module, an intermediate frequency filter module, an ADC and an FPGA, the radio frequency receiving module receives communication signals and control signals from the FPGA, the output of the radio frequency receiving module is connected with the intermediate frequency filter module, the output of the intermediate frequency filter module is connected with the FPGA through the ADC, the gain control output of the FPGA is connected with the radio frequency receiving module, the FPGA further outputs demodulation data, the FPGA comprises a down-conversion module, an AGC control module, a decimal extraction module, a matched filter module, a bit synchronization module, a frequency offset synchronization module, a frequency domain balancing module, a decoding/judging module, a de-interleaving module and a constant-speed buffer module. The receiving terminal and method for the ground-air broadband communication system for the unmanned aerial vehicle can perfect the ground-air broadband signal communication sub-systems and methods of remote measuring, remote control and data transmission systems and methods for the unmanned aerial vehicle, and the receiving terminal and method for the ground-air broadband communication system for the unmanned aerial vehicle can also be suitable for hand-held terminals and vehicle-mounted terminals on the ground.

Receiving terminal and method for ground-air broadband communication system for unmanned aerial vehicle

The invention discloses an inverse synthetic aperture radar (ISAR) parallel processing method. First of all, performing parallel processing of a range-direction compression algorithm on input data to obtain a one-dimensional distance image; then, performing parallel processing of an envelope aligning algorithm on the one-dimensional distance image to obtain a well aligned one-dimensional distance image; and finally, performing parallel processing of an orientation-direction compression algorithm on the well aligned one-dimensional distance image so as to obtain an ISAR image. The ISAR parallel processing method provided by the invention has the advantages of simple realization and remarkable effect. When the parallel processing method is used for performing ISAR imaging on the same segment of data, the algorithm highest parallel efficiency can reach more than 90%. Compared to a conventional imaging method, the imaging real-time performance can be enhanced, the method is simple and is easy to operate, and the imaging cost is decreased.

Inverse synthetic aperture radar (ISAR) parallel processing method

The invention discloses a receiving terminal for an unmanned aerial vehicle land-to-air wideband communication system. The receiving terminal comprises a radio frequency receiving module, a medium frequency filtering module, an ADC and an FPGA. The radio frequency receiving module receives communication signals and control signals from the FPGA. The output of the radio frequency receiving module is connected with the medium frequency filtering module. The output of the medium frequency filtering module is connected with the FPGA through the ADC. The gain control output of the FPGA is connected with the radio frequency receiving module. FPGA outputs demodulation data. The FPGA comprises a lower frequency changing module, an AGC control module, a decimal extracting module, a matching filtering module, a bit synchronization module, a frequency offset synchronization module, a frequency domain balance module, a decoding/judging module, a de-interweaving module and an even-speed buffering module. A land-to-air communication subsystem which can carry out telemetering, remote control and data transmission in the unmanned aerial vehicle system is improved, and meanwhile the receiving terminal is suitable for a handheld terminal and a vehicle-mounted terminal on the ground.

Receiving terminal for unmanned aerial vehicle land-to-air wideband communication system

The invention discloses a small-sized high-speed large dynamic digital receiver system and method. The receiver system comprises a digital analog conversion part and a signal extraction part; the digital analog conversion part adopts an ADC (analog to digital converter) chip; the output of the ADC chip is connected with an FPGA (field programmable gate array) chip logic functional module; the signal extraction part adopts an FPGA chip; the FPGA chip comprises and is sequentially provided with a data conversion module, two levels of FIFO (first in first out) modules, an FFT (fast Fourier transform) module and a super resolution compensation module; a gigabit Ethernet is connected to perform signal outputting after signal extraction. The realizing method of the small-sizes high-speed large dynamic digital receiver system comprises the steps of performing digital analog conversion on a radar simulation signal by the ADC chip, realizing the large dynamic wideband receiving and super resolution compensation processing by the FPGA chip, detecting and sorting the signals in the frequency band, and extracting one or more target signals. The small-sizes high-speed large dynamic digital receiver system is simple in structure, small in size, low in power consumption and strong in hardware reliability, can achieve 10bit sampling bit wide and 4GHz sampling rate, can be used for extracting one or more signals at the same time, and can be applied to multiple fields of radar countermeasure, remote sensing and the like.

Small-sized high-speed large dynamic digital receiver system and method

The invention discloses an FPGA based ISAP imaging parallel envelope alignment method. The method comprises performing FFT, eight-time zero padding and IFFT processing on range data, wherein processed data are output as the result if the processed data are a first group of radar data, otherwise, the data are not output; performing modulus calculation, square root extraction and FFT processing on the data, determining whether the processed data are the first group of radar data, saving the data into the FIFO and jumping to the entrance position if the data are the first group of radar data, and performing complex conjugate multiplication on the data and the previous group of data saved in the FIFO to calculate a modified function if the data are not the first group of radar data; multiplying the modified function by the group of echo data; performing IFFT to obtain results of the group after envelope alignment; performing modulus calculation, square root extraction and FFT processing on the group of results, storing the results in the FIFO to be used for the next group of data, and repeating the steps till all echo data are processed. According to the method, FPGA based parallel radar signal envelope alignment is mainly achieved, high accuracy and the high real-time property of ISAR imaging are achieved, the scheme is simple, power consumption is low, and the processing speed is high.

Field programmable gate array (FPGA) based inverse synthetic aperture radar (ISAP) imaging parallel envelope alignment method

A new miniature linear frequency-modulated continuous-wave radar which mounted on an unmanned aerial vehicle is presented. It allows the accomplishment of high resolution synthetic aperture radar imaging in real-time. Only a Kintex-7 field programmable gate array from Xilinx is utilized for whole signal processing of sophisticated radar imaging algorithms. The proposed hardware architecture achieves remarkable improvement in integration, power consumption, volume, and computing performance over its predecessor designs. The realized design is verified by flight campaigns.

Real-time implementation of frequency-modulated continuous-wave synthetic aperture radar imaging using field programmable gate array

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Small-sized high-speed large dynamic digital receiver system and method

Field programmable gate array (FPGA) based inverse synthetic aperture radar (ISAP) imaging parallel envelope alignment method

Real-time implementation of frequency-modulated continuous-wave synthetic aperture radar imaging using field programmable gate array