PROBLEM TO BE SOLVED: To provide an enciphering method, which enables speedy enciphering and further disables deciphering due to a third party, and an enciphering system using this method. SOLUTION: In this enciphering/deciphering method, a random number sequence Ri is generated on the basis of an applied multiple affine key K, and enciphering is performed by exclusively ORing this random number sequence Ri and a plaintext ABC or the like. Further, this multiple affine key K is automatically and successively reloaded into sequences K', K"... of new multiple affine keys for every prescribed number of times of use and following plaintext DEF... can be continuously enciphered through the generation of random numbers by the sequences of reloaded multiple affine keys. In the case of deciphering, it is similarly performed while using the multiple affine keys to be automatically self-reloaded for every prescribed number of times of use so that the third party can not reproduce this multiple affine key and can not decipher the cipher text.

Enciphering/deciphering method using multiple affine key, authenticating method and each device using the same

PROBLEM TO BE SOLVED: To realize an encryption apparatus capable of improving immunity to a power analysis attack so as to more improve difficulty of decryption. SOLUTION: By inserting dummy DES operation in the middle of main DES operation, it becomes difficult to specify an execution timing of the main DES operation and by providing a first XOR section 31 which uses output data fn of an (f) function of DES to carry out XOR operation, an inverter 33 for inverting bits of the output data fn and a second XOR section 34 which uses the bit-inverted output data fn to carry out the XOR operation, a hamming weight inside an encryption apparatus is fixed without depending upon a value of the output data fn, thereby approximately fixing power consumption in the case of encryption. COPYRIGHT: (C)2006,JPO&NCIPI

Encryption apparatus and semiconductor integrated circuit

PURPOSE: To prevent an output signal from having the same logic continuously by providing a counter which monitors the frequency of continuation of the same logical bit of the output signal to a transmission line encoding circuit wherein bits "1" and "0" are equal in appearance probability. CONSTITUTION: The same signal of the output signal 20 is inputted to a delay element 14 a prescribed delay time later, so the output of an exclusive OR gate 42 is "0" when the same logic bit continues in the output signal 20 and "1" when different logic bits continue. A counter 31 is reset with the output of "1" of the gate 42 to count outputs of "0", the counted value of the counter 31 indicates the continuation of bits with the same logic in the output signal 20. Therefore, when the value of the counter 31 exceeds a prescribed value, a signal of "1" is outputted and a gate 41 inverts the logic of a control signal (output of gate 23) to prevent the continuation of the number of bits with the same logic in the output signal 20. COPYRIGHT: (C)1985,JPO&Japio

Transmission line encoding circuit

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Transmission line encoding circuit