Methods and apparatus are described for facilitating physical synthesis of a circuit design. The circuit design includes a plurality cell instances organized hierarchically. Each cell instance corresponds schematically to one of a plurality of cell types. Transistors in each of the cell instances is sized with reference to an objective function thereby resulting in a first plurality of cell subtypes for each cell type. Each cell subtype corresponding to a particular cell type differs from all other cell subtypes corresponding to the particular cell type by at least one transistor dimension. Selected ones of the subtypes for at least one of the cell types are merged thereby resulting in a second plurality of subtypes for the at least one of the cell types. The second plurality of subtypes being fewer than the first plurality of subtypes. The merging of the selected subtypes achieves a balance between the objective function and a cost associated with maintaining the selected subtypes distinct.

Optimization of cell subtypes in a hierarchical design flow

A very efficient gate array core cell in which the base core cell consists of a group of 6 PMOS transistors and a group of 6 NMOS transistors. It also includes pre-wiring of 2 of the 6 PMOS transistors, with 2 of the 6 NMOS transistors at polysilicon level or at local interconnect level while leaving the remaining PMOS and NMOS transistors as individual transistors to be interconnected during the functional ASIC metallization process. The core cell also has 2 polysilicon or local interconnect wires embedded in it, which can be used to interconnect transistors for logic function implementation. The core cell defined in this invention is highly flexible and has been analyzed to interconnect all types of logic and memory functions needed for ASIC designs. The layout of the transistors, pre-wiring of the strategic transistors at polysilicon level or at local interconnect level, and embedded polysilicon or local interconnect wires reduce the core cell size significantly. This core cell design reduces the overall wiring lengths, parasitic capacitance, which in turn reduce delays, power dissipation and increase ASIC performance and circuit density. Gate array ASIC components designed using this core cell provide circuit density, performance and power dissipation characteristics comparable to the Standard Cell ASICs but with the advantage of reducing the mask cost and processing time by about 50 percent.

Gate array core cell for VLSI ASIC devices

Disclosed herein is an ASIC having a base array of function blocks. Each function block includes a plurality of primitive cells. Each primitive cell is defined by a component from a standard cell library. The base array is prefabricated for use later with a custom circuit design.

Modular array defined by standard cell logic

A programmable semiconductor device includes a user programmable switch comprising a configurable element positioned above a transistor material layer deposited on a substrate layer.

Programmable structured arrays

A cell circuit and corresponding layout is disclosed to include linear-shaped diffusion fins defined to extend over a substrate in a first direction so as to extend parallel to each other. Each of the linear-shaped diffusion fins is defined to project upward from the substrate along their extent in the first direction. A number of gate level structures are defined to extend in a conformal manner over some of the number of linear-shaped diffusion fins. Portions of each gate level structure that extend over any of the linear-shaped diffusion fins extend in a second direction that is substantially perpendicular to the first direction. Portions of each gate level structure that extend over any of the linear-shaped diffusion fins form gate electrodes of a corresponding transistor. The diffusion fins and gate level structures can be placed in accordance with a diffusion fin virtual grate and a gate level virtual grate, respectively.

Cell circuit and layout with linear finfet structures

A user customizable integrated circuit architecture having separate regions for different types of core cells. In an embodiment of the present invention, all asynchronous core cells are placed in a first region and all synchronous core cells are placed in a second region thus allowing clock circuitry to be shared and clock traces to be efficiently routed. Clock buffers may also be placed in the second region. In a second embodiment, high-drive buffers are placed in the second region to enable efficient routing of high-drive power traces to the synchronous cells. Each region also may include metal programmable core cells that may be customized by the user for each design.

Routing driven, metal programmable integrated circuit architecture with multiple types of core cells

A standard cell architecture with a basic cell that spans multiple rows of the standard cell This multi-row basic cell may be a dual-height cell that spans two rows, or it may span more than two rows The multi-row basic cell may be intermixed in a standard cell design with smaller, single-height cells for high-density applications The single-height cells may be used where possible and higher-drive dual-height basic cells where larger transistors are desired Other multiple height cells may also be included if even more current is desirable The power rail may include conductors of varying width

Dual-height cell with variable width power rail architecture

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Routing driven, metal programmable integrated circuit architecture with multiple types of core cells

Dual-height cell with variable width power rail architecture