Direct delta-sigma receiver architecture is introduced for wireless communication systems, such as LTE or WiMax. Architecture is based on direct downconversion, delta-sigma feedback that is up-converted to RF, and N-path filtering technique. Hence, the core receiver functions including channel selection filtering are embedded to a RF ADC with excellent linearity performance. This is achieved by transforming narrow-band filtering partially to RF injecting feedback into the input of the second amplifier stage, hence relieving requirements of the most critical subsequent stages. A 900-MHz direct delta-sigma receiver prototype occupies an active area of 1.2 mm2 in 65-nm CMOS. The receiver for low-band cellular operations achieves NF of 2.3 and 6.2 dB in conventional and delta-sigma modes, respectively, and out-of-band IIP3 up to +4 dBm when the delta-sigma loop is active. The chip consumes 80 mW from a 1.2-V supply.

A 900-MHz Direct Delta-Sigma Receiver in 65-nm CMOS

As global 3G shipment catches up with GSM/EDGE and becomes the mainstream of cellular, a drastic reduction of the cost premium in 3G eBOM becomes imperative, where the RF subsystem features prominently. Full Duplex operation has so far necessitated external LNAs and inter-stage SAW filters in both Tx and Rx paths in commercial 3G phones. Recent publications, where techniques have been proposed to improve RF transceiver design, to enable Tx [1–5] or Rx [5–8] SAW filters to be removed, highlight the attention they now attract from the industry. Here we report a WCDMA transceiver (XCVR), complete with on-chip LNAs and free of both Rx and Tx SAW filters without resorting to calibration or above-passivation inductors, and having reached proven maturity in volume production. Integration of DC-DC converters not only takes eBOM reduction a step further, but also marks a breakthrough by such a noisy function into a cellular RF XCVR of the most sensitive kind in terms of spurious response.

A tri-band SAW-less WCDMA/HSPA RF CMOS transceiver with on-chip DC-DC converter connectable to battery

A robust digitally assisted self-calibration technique is presented to improve the input-referred second-order-intermodulation intercept point (IIP2) of direct-conversion receivers. The low-power, low-noise 1.8-GHz CMOS receiver prototype relies on digital signal processing to improve analog/RF performance with only a minimum hardware overhead and with no performance penalties on the RF front end and analog baseband. The RF front end achieves an IIP2 better than 60 dBm without external filters between the LNA and downconversion mixers, has a conversion gain of 38.5 dB, a low DSB noise figure of 2.6 dB, and an IIP3 of -17.6 dBm. It consumes 15 mA from a 1.5-V supply, and occupies 1.56 mm2 on a 0.13-μm CMOS process.

Digitally Assisted IIP2 Calibration for CMOS Direct-Conversion Receivers

Multi-standard connectivity has become de-facto for smart phones and laptops but is emerging also to other more specialized gadgets like e-book readers. Such devices need to be designed for the best performance even when multiple standards are operating simultaneously. In the future, RF band allocations will make the scene even more complex especially in LTE evolution towards band aggregation. Once RF transceiver architectures have evolved to be compliant with modern CMOS processes new challenges will rise to guarantee smooth user experience in high-speed applications independently of protocol or frequency band. This means stricter requirements in mutual interference and miniaturization from antenna to ASIC's. However, interplay between protocols may also open new opportunities to consider transceiver architecture options suitable for multi-standard radios.

Multimode-multiband transceivers for next generation of wireless communications

A Digitally Controlled Oscillator (DCO) whose power consumption can be reconfigured while maintaining an almost constant phase-noise figure-of-merit (FoM). This is achieved by using either a single-switch-pair or a complementary (i.e., double-switch-pair) oscillator topology, without disturbing the optimized LC tank of the DCO. The optimal power consumption in the complementary (P-N) configuration is reduced by 75% compared to the single-switch-pair (N-only) configuration, while the FoM is kept constant. Measurements on a 55 nm CMOS 4 GHz DCO prototype show a minimum phase noise of -129.3 dBc/Hz at 2 MHz offset from the carrier in the P-N configuration, and of -134.7 dBc/Hz in the N-only configuration, with a phase noise difference very close to the 6 dB expected from theory. The current consumption is 6 mA and 24 mA, respectively, resulting in approximately the same FoM of -185 dBc/Hz.

A Power-Scalable DCO for Multi-Standard GSM/WCDMA Frequency Synthesizers

The large commercial success of multiband multimode 3rd-generation cellular products has driven single-chip integration, SAW-filter reduction and low power consumption. State-of-the-art solutions require quad-band EGSM combined with multiband WCDMA/HSPA receiver diversity and integrated GPS. Compact form factors make single-chip SAW-less solutions highly desirable. A Quad-Band GSM/EDGE-only transceiver was published in [1], and Triple-Band WCDMA-only transceiver solutions were published in [2–4]. This work describes the first multiband WCDMA/HSPA/EGPRS single-chip transceiver with GPS and receiver diversity. This device supports UMTS Bands 1,2,3,4,5,6,8,9,10 and GSM/EDGE 800, 900, 1800, 1900MHz Bands. It is implemented in cost-effective 0.18µm RF CMOS technology and uses a reduced number of TX and RX SAW filters.

Single-chip RF CMOS UMTS/EGSM transceiver with integrated receive diversity and GPS

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Single-chip RF CMOS UMTS/EGSM transceiver with integrated receive diversity and GPS