A method and apparatus to reduce occurrences of electrically non-functional elements, known as dummy features, from a source data structure is described. The source data structure may be image data, a vector based data structure or some other data format. Dummy features in the source data structure are detected and then deleted. Dummy features may be detected by selecting a representative dummy feature, using it as a reference pattern or polygon and comparing it to features in the source data structure. The step of comparing the selected reference to the comprises selecting a cut-off correlation threshold value, and computing the correlation coefficients between the reference and the feature. Features are selectively removed based on a comparison between their correlation coefficients and the selected cut-off correlation threshold value. This threshold value may require updating to remove all dummy features in the source data structure. When different shaped dummy features in the same data structure are encountered, a further reference feature may be selected and the process repeated.

Method and apparatus for removing dummy features from a data structure

The method and apparatus in accordance with the present invention reduces the data size of a layout data structure by reducing the amount of electrically redundant interconnects within a bank of interconnects. Electrically redundant interconnects are the repetitive interconnects within a bank of interconnects which do not contribute to the understanding of the IC. Therefore, a number of these interconnects may be deleted from the banks in the layout data structure, provided that enough interconnects remain to maintain the electrical connectivity and the visual representation of the bank.

Method and apparatus for reducing redundant data in a layout data structure

A method ( 10 ) for compressing a data structure representing a layout of a multi layered VLSI device, the method comprising of the steps of; ( 11 ) Receiving the data structure; said data structure comprising a plurality of layer portions, each layer portion represents a single layer out of the plurality of layers; each layer comprises of functional elements and non functional elements, where the non functional elements are inserted between functional elements to provide a planar layout. ( 12 ) Generating a non-functional elements locating data structure representing the non functional elements of all layers. ( 13 ) Deleting representations of non functional elements from the data structure and adding the compressed non functional elements data structure to generate a compressed data structure representing the layout of the multi layered VLSI device.

Method for compressing a data structure representing a layout of a VLSI device

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Method for compressing a data structure representing a layout of a VLSI device