PURPOSE:To hold the delay time among the circuit elements within the prescribed delay allowable value by a method wherein the connection information is modified by adjusting the number of the loads of the circuit elements using the auxiliary circuit element after arrangement, or the wideness of the wiring and the wiring material are selected. CONSTITUTION:As circuit elements 8, 9, 10, 11 and X are respectively a connection changeable element, the connection between a circuit element 6 and the circuit element 10 and the connection between the circuit element 10 and a terminal 14 are removed. Then, the connection between the auxiliary circuit elements X and the terminal 14 and the connection between a circuit element 7 and the circuit element 10 are anew produced. Hereby the wiring length of a signal A is shortened from l1+l2+l3 to l1+l2, and moreover, the number of the charges of the element 6 is reduced from 3 to 2 in this case and the delay time between the element 6 and the element X is shortened. Then the respective delay times between a terminal 12 and terminals 13, 14...17 are calculated to judge whether or not each section is within the allowable value. When some one among the sections is not within the allowable value, a change in the connection is again executed including the sections within the prescribed allowable value, and when the sections are all within the prescribed allowable value, the change is finished. Reversely, when the delay time is smaller than the prescribed allowable value, a change in the similar processing and connection is reversely executed.

Signal propagation delay adjusting system

PURPOSE:To suppress the transmission delay of signals due to a signal line for a very large scale integrated VLSI circuit by inserting a delay suppressing circuit to the middle of a signal line which connects the 1st and 2nd circuit element regions. CONSTITUTION:A delay suppressing circuit 40 is inserted to the middle of a signal line 30 which connects the 1st and 2nd circuit element regions 10 and 20. Thus the line 30 is divided down to half. As a result, the delay between the region 10 and the circuit 40 is equal to Cp.Rp/4, where Cp and Rp show the parasitic capacity and the resistance value of the line 30 respectively. In the same way, the delay between the circuit 40 and the region 20 is equal to Cp.Rp/ 4. Therefore the total delay is equal to tau+Cp.Rp/2, where tau shows the delay of the circuit 40. Thus the transmission delay of signals can be reduced down to half by setting the tau at a small value. The inserting positions and the number of circuits 40 differ by various modes. Thus it is possible to suppress the transmission delay of signals due to a signal line for a VLSI.

Very large scale integrated circuit

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Very large scale integrated circuit