A memory cell array has a first and a second storage area. The first storage area has a memory elements selected by an address signal. The second storage area has a memory elements selected by a control signal. A control circuit has a fuse element. When the fuse element has been blown, the control circuit inhibits at least one of writing and erasing from being done on the second storage area.

Nonvolatile Semiconductor Memory Device

A method for fabricating a semiconductor device includes forming a recess gate over a semiconductor substrate. A gate spacer is formed on a sidewall of the recess gate. The semiconductor substrate in a landing plug contact region is soft-etched to form a recess having a rounded profile. A sidewall spacer is formed over the gate spacer and a sidewall of the recess. An insulating film is formed over the semiconductor substrate. The insulating film is selectively etched to form a landing plug contact hole. A conductive layer in the landing plug contact hole is filled to form a landing plug.

Semiconductor Device and Method for Fabricating the Same

Disclosed is a method of verifying a programmed condition of a flash memory device, being comprised of: determining a level of an additional verifying voltage in response to the number of programming/erasing cycles of memory cells; conducting a verifying operation to programmed memory cells with an initial verifying voltage lower than the additional verifying voltage; and selectively conducting an additional verifying operation with the additional verifying voltage to the program-verified memory cells in response to the number of programming/erasing cycles.

Flash memory devices that utilize age-based verify voltages to increase data reliability and methods of operating same

In manufacturing a semiconductor device, static electricity is generated while contact holes are formed in an interlayer insulating film by dry etching. Damage to a pixel region or a driving circuit region due to travel of the static electricity generated is prevented. Gate signal lines are spaced apart from each other above a crystalline semiconductor film. Therefore a first protective circuit is not electrically connected when contact holes are opened in an interlayer insulating film. The static electricity generated during dry etching for opening the contact holes moves from the gate signal line, damages a gate insulating film, passes the crystalline semiconductor film, and again damages the gate insulating film before it reaches the gate signal line. As the static electricity generated during the dry etching damages the first protective circuit, the energy of the static electricity is reduced until it loses the capacity of damaging a driving circuit TFT. The driving circuit TFT is thus prevented from suffering electrostatic discharge damage.

Semiconductor Device and Method of Manufacturing the Same

A single crystal semiconductor layer is provided over a base substrate with a second insulating film, a first conductive film, and a first insulating film interposed therebetween; an impurity element having one conductivity type is selectively added to the single crystal semiconductor layer, using a first resist mask; the first resist mask is removed; a second conductive film is formed over the single crystal semiconductor layer; a second resist mask having a depression is formed over the second conductive film; a first etching is performed on the first insulating film, the first conductive film, the second insulating film, the single crystal semiconductor layer, and the second conductive film, using the second resist mask; and a second etching with accompanying side-etching is performed on a part of the first conductive film to form a pattern of a gate electrode layer.

Manufacturing Method of Semiconductor Device

PROBLEM TO BE SOLVED: To provide a method for manufacturing a MOS device at a low cost, which has a high breakdown voltage MOS transistor and a low breakdown voltage MOS transistor. SOLUTION: An N type semiconductor region 14 whose impurity concentration is low, and a P type semiconductor region 13 whose impurity concentration is low, are formed simultaneously to a high breakdown voltage NMOS transistor and a low breakdown voltage NMOS transistor, and N semiconductor regions 15 whose impurity concentration is low are formed simultaneously to the high breakdown voltage NMOS transistor and a low breakdown voltage PMOS transistor, thereby reducing ion implantation process and a photomask necessary for it.

Method for manufacturing semiconductor integrated circuit device

PROBLEM TO BE SOLVED: To prevent delay of a time required for rewriting data and to prevent erroneous discrimination of the data by supplying optimum verify-voltage in accordance with the number of times of rewriting the data. SOLUTION: In the semiconductor integrated circuit device, at the time of rewriting operation of a flash memory, a rewriting number of times discrimination control circuit 15 reads out data of the number of times of rewriting for each sector from a rewriting number of times storing region 14, and outputs a verify-voltage control signal and a switching control signal in accordance with the above to a verify-voltage output circuit 17 and a switching circuit 18. The verify-voltage output circuit 17 selects verify-voltage being suitable for each sector out of verify-voltage V0-Vn generated by a verify-voltage generating circuit 16 and output it to the switching circuit 18. The switching circuit 18 switches an objective of output of the inputted verify-voltage based on a switching control signal, and output is so that the verify-voltage being optimum for each sector is supplied.

Semiconductor integrated circuit device, and supply method of verify-voltage

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Method for manufacturing semiconductor integrated circuit device

Semiconductor integrated circuit device, and supply method of verify-voltage