A method and apparatus for managing spare partition units in a partitionable computing device is disclosed. The method comprises detecting if a spare partition unit is required for addition or replacement in a local operating system and if a spare partition unit is required for addition, initiating an addition of a spare partition unit. If a spare partition unit is required for replacement, a replacement of a failing partition unit with a spare partition unit is initiated; part of the memory of the failing partition unit is passively migrated into the memory of the spare partition unit's partition; part of the memory of the failing partition unit is also actively migrated into the memory of the spare partition unit's partition; and the partitionable computing device is cleaned up. Partition units are replaced without requiring that computer-executable instructions be recompiled.

Replacing system hardware

A method and apparatus for correlating the identities of hardware devices, such as processors and memory controllers, between a local operating system and a global management entity is described. When the operating system detects a faulting device, the operating system generates a fault message and transmits the fault message to the global management entity. The global management entity determines the identity of the faulting device based on information contained in the fault message, selects an appropriate replacement device, changes a routing table to map to the replacement device to the identity of the faulting device, and transmits to the operating system a global identity of the replacement device. The operating system correlates the local identity of the replacement device with the global identity of the replacement device.

Correlating hardware devices between local operating system and global management entity

A technique to enable efficient interrupt communication within a computer system. In one embodiment, an advanced programmable interrupt controller (APIC) is interfaced via a set of of bits within an APIC interface register using various interface instructions or operations, without using memory-mapped input/output (MMIO).

Technique for communicating interrupts in a computer system

In one embodiment, the present invention includes a method for accessing a task stored in an entry of a task queue that identifies the task and a first core of a processor on which the task has been scheduled, reassigning the task to a coldest idle core of the processor, and sending the task to the coldest idle core and maintaining the processor in a turbo mode. Other embodiments are described and claimed.

Increasing turbo mode residency of a processor

Advanced programmable interrupt control for a multithreaded multicore processor that supports software compatible with x86 processors. Embodiments provide interrupt control for increased threads with minimal additional hardware by including in each processor core, a core advanced interrupt controller (core APIC) configured to determine a lowest priority thread of its corresponding processor core. Each core APIC reports its lowest priority thread level as a core priority to an input/output APIC. The I/O APIC routes interrupt requests to the core APIC with the lowest core priority. The selected core APIC then routes the interrupt request to the corresponding lowest priority thread. Each core APIC detects changes in priority levels of its corresponding processor core threads, and notifies the I/O APIC of any change to the corresponding core priority. Each core APIC may notify the I/O APIC as the core priority changes, or when the I/O APIC requests status from each core APIC.

APIC implementation for a highly-threaded x86 processor

An advanced programmable interrupt controller (APIC) identification (ID) configuration method is applied to a multiprocessor computer system. The method assigns a postponed ID to each CPU's APIC IDs respectively during the initialization. Plural reserved IDs are assigned to the I/O APICs. A multiprocessor configuration table in a basic input output system (BIOS) will be updated with renewed ID configuration, to avoid an ID conflict when processing the interrupt request from the peripheral devices and raise the stability of the multiprocessor computer system.

ID configuration method for advanced programmable interrupt controller

The invention is an identification code configuring method for advanced programmable interrupt controllers, applied to a multiprocessor computer system, reallocating identification code of advanced programmable interrupt controller of each CPU in the initializing course, presetting partial identification codes to I/O advanced programmable interrupt controllers and updating multiprocessor configuration table in basic I/O system (BIOS) to avoid the problem of causing identification code conflict at the time of processing interrupt request of peripheral devices, and improving the stability of the multiprocessor computer system.

Identifying-code configuration method of high-grade programable interruption controller

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ID configuration method for advanced programmable interrupt controller

Identifying-code configuration method of high-grade programable interruption controller