This paper presents a new compact CMOS capacitance multiplier. The multiplier is based on using the translinear principle with MOSFETs operating in subthreshold region. The multiplication factor is controllable to meet the designer requirements. Tanner TSPICE simulator was used to confirm the functionality of the design in 0.18 µm CMOS Technology. The circuit operates from ±0.75 supply voltage. Simulation results indicate that the multiplication factor can be varied from 10 to 300. The functionality of the proposed capacitance multiplier was demonstrated by using it in designing a low pass filter and a relaxation oscillator.

A new compact CMOS C-multiplier

A Source Follower based Symmetrical Floating Impedance Scaler (SF-SFIS) circuits are reported in the prior works, which realize large capacitors with the low area for a fully differential filter. In this paper, a novel Flipped Voltage Follower based Symmetrical Floating Impedance Scaler (FVF-SFIS) with high accuracy is presented. The proposed circuit based on flipped voltage follower with cascaded current mirrors can detect low base capacitors which have lower area and power than the prior SF-SFIS circuits. In order to evaluate its performance and comparison, a 500 pF capacitor is realized by multiplying the base capacitor of 10 pF using both FVF-SFIS and SF-SFIS methods. The magnitude and phase of these impedance scalers are obtained through post-layout simulation. It is found that the proposed impedance scaler requires 51.58% lower area, 69.23% lower power dissipation, and 91.33% higher accuracy than the SF-SFIS. The accuracy of the proposed FVF-SFIS is compared with SF-SFIS circuit by designing a 3rd order Chebyshev low pass filter (LPF) using FVF-SFIS and SF-SFIS with cut-off frequency 100 Hz. The circuit has been designed and simulated in UMC 180 nm technology.

Area and power efficient flipped voltage follower based symmetrical floating impedance scaler with improved accuracy for fully differential filters

Two novel OTA based grounded capacitor multiplier circuits are proposed. First capacitance multiplier circuit is based on OTA based impedance multiplier reported earlier. Other capacitance multiplier is an improved version of the current-mode capacitance multiplier reported earlier, where in the DO-OTA is used instead of current mirror which senses the input current and scales it by a factor (k+1) such that a scaled version of input current flows through the capacitor (I c = I in /(k+l)). The first capacitance multiplier uses grounded capacitor and the second one uses a floating capacitor. The capacitor multiplier circuits are verified using TINA SPICE simulator.

Novel large value grounded capacitor realizations using OTAs and small capacitors

Capacitors realized using symmetric floating impedance scaling (SFIS) are area efficient. They are preferred for the implementation of fully differential filters for biomedical applications. The SFIS reported in the literature has poor accuracy and lower effective bandwidth. In this paper, a cross coupled symmetric floating impedance scaling (CC-SFIS) with enhanced bandwidth and accuracy is proposed. To evaluate its performance, a 500 pF capacitor is implemented in UMC 180 nm CMOS technology with a base capacitor ( C b ) of 10 pF using both CC-SFIS and source follower based SFIS (SF-SFIS). The magnitude and phase of the impedance of the capacitor realized using CC-SFIS and SF-SFIS are obtained through post-layout simulations. CC-SFIS requires 53.68% lower area, 62.39% lower power consumption, and 88% higher accuracy than SF-SFIS. Fully differential 2nd order Butterworth low pass filters with cutoff frequency of 100 Hz are implemented in UMC 180 nm technology using both CC-SFIS and SF-SFIS capacitors. Their performances are evaluated through simulation. From this, it is found that the deviation in the cut off frequency of the filter using CC-SFIS is smaller (2%) compared to that using SF-SFIS (40%) circuit.

A cross-coupled symmetric floating impedance scaler with enhanced bandwidth and accuracy

This paper presents a new compact CMOS capacitance multiplier. The multiplier is based on using the trnaslinear principle. Only four MOSFETs operating in subthreshold region are used. The multiplication factor is controllable to meet the designer requirements. Tanner TSPICE simulator is used to confirm the functionality of the design in 0.18μm CMOS Technology. The circuit operates from ±0.75 supply voltage. Simulation results indicate that the multiplication factor is large compared to existing designs. The functionality of the proposed capacitance multiplier is demonstrated by using it in designing relaxation oscillator.

A new controllable CMOS impedance scaler

A capacitor multiplier with large multiplication factor based on dual-output differential amplifiers is presented. The proposed circuit consists on multiple stages connected in series to provide a large multiplication factor, formed by transconductance differential amplifiers with dual outputs where one of the outputs provides a scaled current with respect to the other by a factor k. Simulation results in 0.5μm technology confirm the proposed operation.

Multiple stage capacitor multiplier using dual-output differential amplifiers

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Multiple stage capacitor multiplier using dual-output differential amplifiers