As transistor size decreases to the deep submicron range and the number of devices per chip approaches one million, testing becomes increasingly challenging and is intensively investigated. This volume gives a comprehensive and timely review of the current status of VLSI testing. The book covers most of the important aspects of VLSI testing, for example, generating test vectors (chapter 3), creating output signatures and self-testing (chapter 4), and designing for built-in testing (chapter 5). It also addresses the special needs and features required for testing highly structured digital circuits, such as memories and PLAs (chapter 6) and some popular analogue circuits (chapter 7). Around eighty percent of the book is devoted to digital circuits, while the remainder deals with analogue and mixed analogue/digital techniques. The book introduces a significant number of testing methods and strategies. Many of them are still under research and are not widely used in practice, and too much attention is paid to these techniques. For the methods that are widely used, the number of worked examples is inadequate. Although the summary at the end of each chapter is useful, there are no questions provided, which one would expect in a textbook. Wafer fabrication tests are also omitted, and there is little information on the causes of failure. The coverage of CMOS testing is limited, considering the increasing dominance of CMOS processes in the semiconductor industry. There are also few details of how tests can be carried out using the popular VLSI CAD facilities, such as CADENCE, used in industry and education. Overall, however, this is a valuable book on VLSI testing.

VLSI Testing: Digital and Mixed Analogue/Digital Techniques

Preparing the books to read every day is enjoyable for many people. However, there are still many people who also don't like reading. This is a problem. But, when you can support others to start reading, it will be better. One of the books that can be recommended for new readers is in circuit testing. This book is not kind of difficult book to read. It can be read and understand by the new readers.

In-circuit testing

In this paper, the incorporation of pseudo-exhaustive built-in self-test capabilities into the boundary scan (BS) architecture is presented. The Boundary Scan Register (BSR) input cells are configured as a test pattern generator (TPG), and the BSR input and output cells are configured as a test response compactor (TRC) in the BIST mode. Instructions for both BS and BIST process are proposed that enable the test access port controller (TAPC) to control the BS and BIST process. The presented design supports the BIST of the target chip for both the cascaded and non-cascaded input and output cells of the BSR. In the register transfer level (RTL), the insertion of segmentation cells in the case of pseudo-exhaustive testing (PET) may affect the system timing due to the unequal sequential depth in the BIST mode, so it is required to insert delay flip-flops which add significant area overhead and degrade circuit performance. In addition, transferring every flip-flop into BIST flip-flop adds area overhead and degrades circuit performance in the normal mode of the chip. To compensate these problems, a proposed design that converts the presented sequential block into the combinational block (combinational equivalent). The incorporation of BIST capabilities into the boundary scan architecture with this solution is presented. Finally, a complete example for BIST (Built-In Self-Test) boundary scan architecture and 16-bit parallel-pipelined multiplier as the CUT is presented. The simulation and then design download are presented on the field programmable gate array (FPGA) chip. The hardware implementation using the interfacing through the personal computer as a master controller controls the test circuitry from the TAPC as a slave controller.

/pdf/new-built-in-self-test-boundary-scan-architectures-for-54j3qkw0x8.pdf

New Built-In Self-Test Boundary Scan Architectures for Digital Integrated Circuits in Industrial Applications

With the trend of electronic products toward multifunctions, miniaturization, and high performance, the advanced packaging and system-on-chip technologies are the main methods to achieve higher added value products. In order to ensure product performance, design technologies become increasingly more important. This chapter summarizes and discusses the key points of design technologies for advanced packaging. According to the performance requirements, different package types and material systems should be selected. Electrical, thermal, and structural designs, even multiphysics analysis, and necessary collaborative designs are needed. 

Design Technologies for Advanced Packaging

In this paper, the application of the board-level external testing using the pseudo-exhaustive testing (PET) was explored. The new design approach to reconfigure the hardware of the pseudo-exhaustive test pattern generator (PETPG), based on the permutated convolved linear feedback shift register/shift register (LFSR/SR), is developed. The permutated convolved LFSR/SR is considered a superset of all previously published output-specific PETPGs in the PET with low test application time (TAT). The PET segments digital circuit-under-test (CUT) into several output cones. The proposed test system can stimulate all combinational hard faults in each output cone using the reconfigured PETPG without the need of the fault simulator, and to compact test responses of digital circuits for signature generation. The simulation results using some digital circuits, compared to previously published works, illustrate the effectiveness of the presented test approach to detect target faults with reduction of TAT.

Reconfigurable PETPG for External Testing of Digital Circuits

Integrated circuits (ICs) are reaching complexity that was hard to imagine. ICs incorporating hundreds of millions of transistors, mega-bit memories, complicated pipelined structures, etc., are in high demand. Obviously, designing such complex circuits poses real challenges to engineers. Certainly, no relief comes from the competitive marketplace, with increasing demands for a very narrow window of time (time-to-market) in engineering a ready product. Therefore, a systematic and well-structured approach to designing ICs to be testable is a must. With the growth in complexity of very large scale integration (VLSI) circuits, test generation for circuits is becoming increasingly difficult and time consuming. Even though the computing power and resources have multiplied dramatically over last few decades, an increasing number of memory elements in VLSI circuits require more effective and powerful sequential test generators. This paper is represented to review concepts and techniques for testing electronic circuits and systems as part of a lecture review. This covers various testing and design-for-test (DFT) techniques starting from (Automatic Test Equipment) ATE basics (definition, construction and types). Exploring testing strategies for digital combinational and sequential circuits, and introduces a comparative study between the common fault models. Finally the paper ends with design for testability guiding rules and possible challenges and difficulties that need development and research in the testing problem.

https://iceeng.journals.ekb.eg/article_33550_f4dc09fe590b17fe9cb191c0ee08fef7.pdf

Design for Testability of Circuits and Systems; An overview

Testing for delay and CMOS stuck-open faults requires two-pattern tests. Built-in self-test (BIST) schemes are required to comprehensive testing of such faults. BIST test pattern generators for two-pattern testing should be designed to ensure high transition coverage. The test pattern generator (TPG) circuits treated here are not limited to linear feedback shift registers (LFSRs) but include autonomous linear feedback shift register / shift register (LFSR/SR) circuits. It is required to increase the number of each subset of the state variables for complete transition coverage with the optimal test lengths.

https://asat.journals.ekb.eg/article_23962_983d97de95bfa15cb3005f76b61b5d6e.pdf

Two-pattern test capabilities of autonomous lfsr/sr generator in pseudo-exhaustive testing

Popular Tasks used by Researchers

How can I help with your research?

Get more enhanced response by uploading the PDFs you want me to reference.

No relevant PDFs in your library

SciSpace is the AI research assistant for academics. Run systematic literature reviews on 280M+ papers, and write papers with cited sources. Trusted by 1M+ students, PhDs & researchers.

SciSpace | AI for Research

We encountered an error while loading the panel. Please try refreshing the page.

Something went wrong

Analyze PDFs

Code & Manuscripts

Funding & Grants

Literature & Patents

Medical & Clinical Data

Systematic Review

Visualize & Present

Web & Data

Build a Google Scholar-like website for your research.

Build a website

Create charts and images for your research

Create a Chart

Write a paper for submission to a journal

Draft a manuscript

Patent Search

Design eye-catching scientific posters in minutes.

Scientific Poster Generation

Systematic Literature Review

Anyone with the link can view this chat. You can switch it back to private anytime.

One task is running at the moment. Your messages will be shown right after.

Drag and drop or click here to browse

Loved by <highlight>1 million+</highlight> researchers

Extract a list of specific topics and their sources from unstructured text

Topics

Compare and analyze relevant papers that matches with your search

Papers

Get insights from PDFs and bookmarked papers from your library

My library

Recent searches

Try searching for:

Catch AI-generated content in scholarly and non-scholarly content

{ai} Detector

Ai Writer

Get PDF Summaries, highlighted text explanations 

Chat with PDF

Effortlessly create in-text citations and bibliographies in APA and 2,500 other formats

Citation generator

Get explanations, summaries, and answers on academic papers

Ease up your research workflow with {scispace}'s cohort of exciting AI tools

Elevate your academic writing skills and convey your ideas the way you want

Paraphraser

Explore our range of reading and writing tools

Your file is being prepared and should be ready in a few minutes. If it's a large file, it might take a bit longer. You can close this window, and we'll email you the file when it's done.

You have reached a maximum limit of <strong>{limit}</strong> columns in the table. Remove at least <strong>1</strong> column to add or create another one.

Emad Khalil

Author Tools

Chat about Author

Papers

Design for Testability of Circuits and Systems; An overview

Two-pattern test capabilities of autonomous lfsr/sr generator in pseudo-exhaustive testing