Mixed analog and digital mode simulators have been available for accurate /spl alpha/-particle-induced transient fault simulation. However, they are not fast enough to simulate a large number of transient faults on a relatively large circuit in a reasonable amount of time. In this paper, we describe a gate-level transient fault simulation environment which has been developed based on realistic fault models. Although the environment was developed for /spl alpha/-particle-induced transient faults, the methodology can be used for any transient fault which can be modeled as a transient pulse of some width. The simulation environment uses a gate level timing fault simulator as well as a zero-delay parallel fault simulator. The timing fault simulator uses logic level models of the actual transient fault phenomenon and latch operation to accurately propagate the fault effects to the latch outputs, after which point the zero-delay parallel fault simulator is used to speed up the simulation without any loss in accuracy. The environment is demonstrated on a set of ISCAS-89 sequential benchmark circuits.

A gate-level simulation environment for alpha-particle-induced transient faults

To study the effect of transient faults in large digital circuits, a simulation tool called DYNAMO has been developed. It allows transient faults to be introduced in a circuit during a transient analysis so that its behavior can be observed and recorded. For efficiency, a dynamic mixed-mode simulation approach is employed whereby the representation of various portions of the circuit may switch between different levels of abstraction during the simulation, as dictated by the location of the transient fault and the resulting behavior of the circuit. Experiments have shown very encouraging results with significant speedups in CPU run times relative to the previous approach. The results of transient-fault simulation using the DYNAMO program on an avionic control microprocessor are also included. >

Simulation and analysis of transient faults in digital circuits

The problem of bridging fault simulation under the conventional voltage testing environment is considered. A method to provide electrical-level simulation accuracy, without paying the associated performance penalties, is proposed. A three-level simulation model is used, balancing the tradeoffs among gate-level, switch-level, and electrical-level simulation. Large memory overheads are avoided by localizing the fault, and by performing electrical-level simulation only in the area around the fault. This approach is sufficiently flexible to model feedback faults, BiCMOS circuits, stuck-open faults, and any fault that can be described with a circuit netlist. Tests were run on several ISCAS combinational and sequential benchmark circuits, using realistic cells and transistor parameters; results show that accurate simulations can be performed in reasonable time. >

E-PROOFS: A CMOS bridging fault simulator

The problem of bridging fault simulation under the conventional voltage testing environment is considered. A method to provide electrical-level simulation accuracy, without paying the associated performance penalties, is proposed. A three-level simulation model is used, balancing the tradeoffs among gate-level, switch-level, and electrical-level simulation. Large memory overheads are avoided by localizing the fault, and by performing electrical-level simulation only in the area around the fault. This approach is sufficiently flexible to model feedback faults, BiCMOS circuits, stuck-open faults, and any fault that can be described with a circuit netlist. Tests were run on several ISCAS combinational and sequential benchmark circuits, using realistic cells and transistor parameters; results show that accurate simulations can be performed in reasonable time.<<ETX>>

E-PROOFS: a CMOS bridging fault simulator

The authors introduce ILLIADS as a fast MOS timing and reliability simulator for very large digital MOS circuits. The use of the proposed general circuit primitive not only provides better accuracy but also significantly reduces the simulation time. The use of an analytic solution embedded in the simulation engine improves both the simulation speed and the accuracy. Postponing the waveform approximation process provides better waveform approximation even for non-fully-switching waveforms and glitches. The channel length modulation effect is captured accurately in fast timing simulation with only 10% of speedup tradeoff. It is also shown that ILLIADS manifests the charge sharing problem. The modified PWCTC algorithm, PWCTC-W, which handles circuits with feedback, is introduced and shown to be superior to the dynamic-windowing scheme. It also does not manifest the window-growing problem and is insensitive to the level of strongly concerned component (SCC) hierarchy. The use of this algorithm keeps the speedup of ILLIADS over SPICE for circuits with feedbacks at the same level as that for combinational circuits. >

ILLIADS: a fast timing and reliability simulator for digital MOS circuits

The techniques used in the iSPLICE3 simulator for the analysis of mixed analog/digital circuits are described. iSPLICE3 combines circuit, switch-level timing, and logic simulation modes and uses event driven selective-trace techniques. It also uses a hierarchical schematic capture package called iSPI (Simulation Program Interface) for design entry, circuit partitioning, and simulation control. The contributions here include a new DC solution method, a mixed-mode interface modeling technique, and an automatic partitioning approach for MOS logic circuits. The details of these three methods are provided, along with the architecture and transient simulation algorithms used in iSPLICE3. The results of circuit simulations and mixed-mode simulations of a CMOS static RAM, two A/D converters, and a phase-locked loop are presented. These results indicate that iSPLICE3 is between one and two orders of magnitude faster than SPICE2 with negligible loss in accuracy. >

Simulation techniques for mixed analog/digital circuits

A simulator called iSPLICE3 is described for the analysis of mixed analog/digital circuits is described. It combines electrical, switch-level timing and logic simulation modes using event-driven selective-trace techniques. This simulator features a hierarchical schematic capture package called iSPI for design entry and simulation control. It uses a novel approach to improve the speed and robustness of the DC solution. The details of the simulator architecture, circuit partitioning, mixed-mode interface, and event scheduling are provided along with the results of mixed-mode simulations of a recently designed memory circuit

iSPLICE3: a new simulator for mixed analog/digital circuits

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Simulation techniques for mixed analog/digital circuits

iSPLICE3: a new simulator for mixed analog/digital circuits