Vertically integrated circuits (3-D ICs) may revitalize Moore’s law scaling which has slowed down in recent years. 3-D stacking is an emerging technology that stacks multiple dies vertically to achieve higher transistor density independent of device scaling. They provide high-density vertical interconnects, which can reduce interconnect power and delay. Moreover, 3-D ICs can integrate disparate circuit technologies into a single chip, thereby unlocking new system-on-chip architectures that do not exist in 2-D technology. While 3-D integration could bring new architectural opportunities and significant performance enhancement, new thermal, power delivery, signal integrity and reliability challenges emerge as power consumption grows, and device density increases. Moreover, the significant expansion of CPU design space in 3-D requires new architectural models and methodologies for design space exploration (DSE). New design tools and methods are required to address these 3-D-specific challenges. This keynote paper focuses on the state of the art, ongoing advances and future challenges of 3-D IC design tools and methods. The primary focus of this paper is TSV-based 3-D ICs, although we also discuss recent advances in monolithic 3-D ICs. The objective of this paper is to provide a unified perspective on the fundamental opportunities and challenges posed by 3-D ICs especially from the context of design tools and methods. We also discuss the methodology of co-design to address more complicated and interdependent design problems in 3-D IC, and conclude with a discussion of the remaining challenges and open problems that must be overcome to make 3-D IC technology commercially viable.

TSV-Based 3-D ICs: Design Methods and Tools

Development of Physically Based Atomistic Microstructures: The Effect on the Mechanical Response of Polycrystals.

Fatigue behaviors of the CoCrFeMnNi-based high-entropy alloy thin foils with different Al addition were investigated under dynamical bending fatigue loading. The results reveal that the Al addition can effectively decrease the cyclic strain localization and improve the fatigue resistance, which is associated with the reduced cyclic slip irreversibility. The physical reasons for such reduction can be attributed to the enhanced planar-slip ability induced by Al addition. Furthermore, the formation of BCC phases caused by 10 at.% Al addition also leads to a delay in the fatigue crack propagation. 

Enhancing bending fatigue resistance of the CoCrFeMnNi high-entropy alloy thin foils by Al addition

Fatigue performance of metallic nanolayered composites (NLCs) has been gaining more and more attention due to the rapid development in the field of both micro-electro-mechanical systems and high-performance engineering structure materials and the increasing demand for long-term fatigue reliability. Metallic NLCs have exhibited different damage behaviors due to the effect of high-density heterogeneous interface compared with bulk materials and thin metal films. In this review paper, the cyclic deformation damage behavior, fatigue cracking feature, and fatigue properties of some metallic NLCs are reviewed. Effects of length scales, including layer thickness and grain size, on fatigue damage behaviors of the NLCs are revealed, and the transition of the fatigue cracking behavior and the corresponding damage mechanism are discussed. Then, the fatigue properties of some typical metallic NLCs are presented and compared with that of bulk materials and metal thin films. The effect of interface type and grain boundary alignment is also discussed to correlate with fatigue cracking resistance of the NLCs. Finally, some prospective research topics on fatigue performance of metallic NLCs are addressed.

A review on cyclic deformation damage and fatigue fracture behavior of metallic nanolayered composites

The development of big data and artificial intelligence technology is increasing the need for electronic devices to become smaller, cheaper, and more energy efficient, while also having enhanced functionalities. However, the miniaturization of silicon chip technology is approaching its Moore's law (i.e., physical) limits. Thus, the application of three-dimensional integrated circuits (3D ICs), in which multiple chips are stacked vertically, provides the most achievable approach for the advancement of post-Moore electronics. In the recent decade, various key techniques have been developed for stacking chips vertically such as through-silicon vias, micro-bumps, low melting point tin–bismuth solders, redistribution layers, and copper-to-copper direct bonding. However, the need for high current densities in these structures results in severe Joule heating, making electromigration (EM) an increasingly challenging problem. This paper reviews studies on EM failures, mechanisms, and potential solutions for the key components of 3D IC packaging.

Electromigration in three-dimensional integrated circuits

TSV is the key component in fabricating 3-D ICs which can bring lower power consumption, higher integration density and shorter interconnection length. Very few works on EM and TDDB of TSV have been done. Thus, TSV macros with BEOL and backside metal were designed and tested adventurously with EM and TDDB reliability perspective. For EM, the void, however, was found at Cu/SiN interface between TSV bottom and backside metal not at TSV itself due to unexpectedly strong reliability of TSV. And also the TDDB occurred at IMD not at TSV dielectric oxide layer. As a result, the minimum level of reliability of TSV has been obtained experimentally in silicon data at least although the reliability of TSV itself has not been assessed exactly. The guide lines for making reliability macros and testing conditions are suggested also by further investigation.

An experimental study on the TSV reliability: Electromigration (EM) and time dependant dielectric breakdown (TDDB)

In this study, intuitive is given on time-dependent thermal characteristics in multilevel interconnects subjected to carry either DC or pulsed-DC. FEM simulation is employed to model the propensity of temperature profile with respect to the variety of interconnects having different geometrical features in terms of metal width, metal height and distance between metal and Si substrate. Accordingly, a practical model that enables to prognosis temperature increase resulting from current-driven metal interconnects and temperature decrease after current carried along metal line stops is developed. It is found that a proposed model precisely predicts thermal transient arisen from metal interconnect, regardless of geometrical factors of metal dimension and location. In addition, transient thermal behavior of metal interconnects carrying pulsed DC with various frequencies is investigated. A circuit designer is required to adjust the maximum allowable current carried along metal interconnects according to the frequency of pulsed DC as well as geometrical dimensions of metal interconnects. Hence, robustness in circuit design even in the earlier stage of development phase can be accomplished for metal interconnects by suppressing electromigration and rupture caused by thermal transient.

A practical modeling for transient thermal characteristics of multilevel interconnects

Early failure of the short-lead metal line EM (Electromigration) is investigated. Applying Wheatstone bridge (WSB) test structure and 3-parameter lognormal distribution enables to reduce sample size and time-to-fail (TTF) variation governed by early fails causing a poor standard deviation, EM lifetime is accurately predicted and improved by ~280×. In particular, EM TTF at lower percentiles can be well represented by 3-parameter lognormal. With respect to physical aspects of void, EM behaviors of the short-lead and long-lead metal line are addressed based on experimental results compared with Monte-Carlo simulations to support the Blech's back-stress effects.

Early failure of short-lead metal line and its EM characterization with Wheatstone bridge test structure in advanced Cu/ULK BEOL process

Fatigue Behavior of Electrodeposited Nanocrystalline Nickel Films

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An experimental study on the TSV reliability: Electromigration (EM) and time dependant dielectric breakdown (TDDB)

A practical modeling for transient thermal characteristics of multilevel interconnects

Early failure of short-lead metal line and its EM characterization with Wheatstone bridge test structure in advanced Cu/ULK BEOL process

Fatigue Behavior of Electrodeposited Nanocrystalline Nickel Films