A sigma-delta (ΣΔ) analog-to-digital converter (ADC) accepts band-limited analog signals, and subtracts an analog replica of an output pulse- or amplitude-density modulated (ADM) signal therefrom to produce an error signal. The error signal is processed by an analog filter or resonator with a nondelayed forward path and a tapped nonaccumulating delay line, and summed feedback and feedforward weights coupled to the taps, to thereby produce a resonated signal. An ADC processes the resonated signal, and produces the ADM signal. The ADC undesirably produces quantization noise. A digital-to-analog converter (DAC) noiselessly converts the PDM signal into the analog replica, to aid in forming the error signal. In a particular embodiment of the invention, the resonator includes a recursive analog transversal filter with delays and linear weighting elements for linearity and high operating speed. The ADC may be in a high-speed system such as a radar.

Sigma-delta analog-to-digital converter with filtration having controlled pole-zero locations, and apparatus therefor

A sigma-delta modulator comprising a low-pass filter of the Nth order, which is constituted by a series combination of N first-order integrating sections (6.1, 6.2, 6.3, . . . , 6.N) each comprising an integrator (12.1, 12.2, 12.3, . . . , 12. N) and a limiter (14.1, 14.2, 14.3, . . . , 14.N). The individual output signals of the sections are weighted by means of corresponding weighting amplifiers (16.1, 16.2, 16.3, . . . , 16.N) and the weighted signals are added together by an adder stage (18). The gains of the sections and the limit values of the limiters are selected so that the last limiter (14.N) in the series arrangement is activated first as the input signal level to the sigma-delta modulator increases, then the last-but-one limiter, and so on. This reduces the order of the filter system each time by one section as the input signal level increases above each successive limit value, thereby causing the sigma-delta modulator to remain stable at all signal levels.

Sigma-delta modulator having a plural order loop filter with successive filter sections of successively smaller signal excursion range

Methods and systems for applying digital dither includes methods and systems for applying digital dither in data converters, such as, for example, delta-sigma data converters. In an embodiment, an analog signal from a first path of a delta-sigma modulator is quantized to an m-bit digital signal and an n-bit dithered digital feedback signal is generated from at least a portion of the m-bit digital signal. The n-bit dithered digital feedback signal is converted to an analog feedback signal and fed back to a second path of the delta-sigma modulator. In an embodiment, the n-bit dithered digital feedback signal is generated by selecting one of a plurality of sets of n-bits from the m-bit digital signal depending upon a state of a dither control signal. The dither control signal can alternate between a plurality of states or pseudo-randomly switch between a plurality of states. In an embodiment, the m-bit digital signal is an m-bit thermometer code signal and the n-bit dithered digital feedback signal is generated by selecting between bits 0 through m−2 and bits 1 through m−1 of the m-bit digital signal. In an alternative embodiment, the m-bit digital signal is an m-bit thermometer code signal and the n-bit dithered digital feedback signal is generated by selecting between even and odd bits of the m-bit digital signal.

Methods and systems for digital dither

The present invention is directed to a sigma-delta digital to analog converted (DAC) including a digital-sigma delta modulator, a decimation filter, and a multi-bit DAC. The digital sigma-delta modulator receives a digital input signal and produces a quantized digital signal therefrom. The decimation filter receives the quantized digital signal and produces a decimated digital signal therefrom. The multi-bit DAC receives the decimated digital signal and produces an analog output signal therefrom. The analog output signal is representative of the digital input signal.

Sigma-delta digital-to-analog converter

In a conventional sigma-delta converter/modulator, quantisation noise of the quantiser which produces the digital output is suppressed because of a feedback loop which feeds an error signal via a filter to the quantiser, the error signal being the difference between the digital output and the input. Improved noise suppression is achieved by more filter stages, but such converter/modulators require special measures to reset them in the event of an overload i.e. a high input signal. A modified output is taken from the filter which is such that a second filter appears, when the main loop is not overloaded, to be in a loop with a simple delay, i.e. a sigma-delta circuit. The main loop has the inherent recovery properties of a second order modulator/converter and cannot be swamped by the signal from the second loop because of a limiter and, when the main loop has recovered, so does the second loop containing second filter. However, the quantisation noise is now suppressed by the combined filters. In an analogue equivalent, the limiter receives a signal representative of each of those filter orders to permit an equivalent impulse response to be provided.

Analogue-to-digital converters and digital modulators

The quantization noise in a delta-sigma converter can produce correlated noise when the converter is operating This correlated noise can produce tones in the frequency band of interest In a departure from conventional wisdom these tones are substantially eliminated by the degration of the signal-to-noise ratio at the input of the comparator in the delta-sigma converter In the preferred embodiment this degradation of the signal-to-noise ratio is accomplished by attenuating the input signal to the comparator such that the input signal becomes comparable to the noise generated in the input stage of the comparator

Method for tone avoidance in delta-sigma converters

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Method for tone avoidance in delta-sigma converters