Various methods and systems for creating or performing a dynamic sampling scheme for a process during which measurements are performed on wafers are provided. One method for creating a dynamic sampling scheme for a process during which measurements are performed on wafers includes performing the measurements on all of the wafers in at least one lot at all measurement spots on the wafers. The method also includes determining an optimal sampling scheme, an enhanced sampling scheme, a reduced sampling scheme, and thresholds for the dynamic sampling scheme for the process based on results of the measurements. The thresholds correspond to values of the measurements at which the optimal sampling scheme, the enhanced sampling scheme, and the reduced sampling scheme are to be used for the process.

Methods and systems for creating or performing a dynamic sampling scheme for a process during which measurements are performed on wafers

In a lithographic apparatus, a slip of a patterning device relative to a support, the support constructed to support the patterning device, may be provided by measuring a position of the support relative to a first structure of the lithographic apparatus; measuring a position of the patterning device relative to a second structure of the lithographic apparatus; determining a correlation between the position of the patterning device and the position of the support from the measured position of the support, the measured position of the patterning device, and the mutual positions of the first and second structures; and deriving from the correlation a slip of the patterning device relative to the support. The structure may include a projection system to project a radiation beam patterned by the patterning device. The projection system may be connected to a frame, such as a metrology frame of the lithographic apparatus.

Lithographic apparatus and method

We report record low $8.4\times 10^{-10}~\Omega $ -cm2 n-type S/D contact resistivity with laser-induced solid/liquid phase epitaxy of Si:P inside nano-scale contact trenches. Significant reduction of device resistance and resultant great gain of drain current has been demonstrated in scaled n-FinFETs with a contact length of 20 nm.

Sub- $10^{-9}~\Omega $ -cm2 n-Type Contact Resistivity for FinFET Technology

A method and apparatus for process control in a lithographic process are described. Metrology may be performed on a substrate either before or after performing a lithographic patterning process on the substrate. One or more correctables to the lithographic patterning process may be generated based on the metrology. The lithographic patterning process performed on the substrate (or a subsequent substrate) may be adjusted with the correctables.

Feedforward/feedback litho process control of stress and overlay

A method for bonding a first wafer on a second wafer by molecular adhesion, where the wafers have an initial radial misalignment between them. The method includes bringing the two wafers into contact so as to initiate the propagation of a bonding wave between the two wafers while a predefined bonding curvature is imposed on at least one of the two wafers during the contacting step as a function of the initial radial misalignment.

Method for molecular adhesion bonding with compensation for radial misalignment

Techniques and systems for using optical interferometers to obtain full-field optical measurements of surfaces, such as surfaces of flat panels, patterned surfaces of wafers and substrates. Applications of various shearing interferometers for measuring surfaces are described.

Full-filled optical measurements of surface properties of panels, substrates and wafers

Provided are methods to be carried out prior to, while, and/or after performing a photolithographic process to a wafer that involve wafer misalignment assessment. The method involves obtaining curvature and/or deformation information of a surface of the wafer over a plurality of locations so as to obtain a curvature map of the wafer. The curvature map is processed to obtain a stress map of the wafer. The stress map is used to determine displacement of a layer of the wafer. The displacement information is used to determine a degree of misalignment in the photolithographic process.

Determination of lithography misalignment based on curvature and stress mapping data of substrates

The use of strained SiGe is essential to improvement in device performance. However, the structure is susceptible to strain relaxation and wafer deformation during thermal annealing. The accumulation of stress in the wafer needs to be controlled to minimize photolithographic overlay errors. Laser spike annealing offers negligible pattern effects, closed-loop temperature control, and localized heating, which help control stress intensity and variation. This paper describes the effect of dwell time on deformation and its contribution to overlay error. By the use of a stress measurement technology, the Coherent Gradient Sensing (CGS) interferometer, a detailed characterization of deformation induced during micro-second laser annealing can be correlated to the overlay error.

Impact of laser spike annealing dwell time on wafer stress and photolithography overlay errors

In advanced lithography, controlling the overlay budget is one of the most critical requirements. For device nodes at 10nm and below, there are many process-based sources of surface displacement that contribute to the lithography overlay budget that are independent of the lithography process, i.e. etch, anneal, CMP, etc. By developing an understanding of how process-induced surface displacement impacts overlay, displacement information can be fed-forward to the lithography tool for overlay correction during the lithography process. This paper describes the use of displacement measurement technology, the Coherent Gradient Sensing (CGS) interferometer, to characterize the effects of process-induced overlay error on the overlay budget through several processes in a typical semiconductor process flow. The CGS technique facilitates the generation of high-density displacement maps (>3 million points on 300mm wafer) such that the stresses induced die-by-die and process-by-process can be tracked in detail. Case studies are presented that summarize the use of the CGS data to reveal correlations between displacement variation and overlay variation, and demonstrate how feed forward can be applied for controlling overlay error.

A study of feed-forward strategies for overlay control in lithography processes using CGS technology

A new dual-beam laser spike annealing (DB-LSA) technology is developed to expand the application space of non-melt laser annealing. In the standard LSA configuration, a single narrow laser beam is used to heat the wafer surface from substrate temperature to the peak annealing temperature close to silicon melt. In DB-LSA, a second wide laser beam is incorporated to preheat the wafer. The dual beam system offers flexibility in tuning the temperature and stress profiles. It also enables lower substrate temperature that is compatible with the middle of line applications. In this paper, we will discuss the new capabilities of DB-LSA. Implications on Rs-Xj scaling, defect curing and silicide formations will also be discussed.

Dual beam laser spike annealing technology

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