The hybrid architecture analysis and design language (AADL) has been proposed to model the interactions between embedded control systems and continuous physical environment. However, the worst-case performance analysis of hybrid AADL designs often leads to overly pessimistic estimations, and is not suitable for accurate reasoning about overall system performance, in particular when the system closely interacts with an uncertain external environment. To address this challenge, this paper proposes a statistical model checking-based framework that can perform quantitative evaluation of uncertainty-aware hybrid AADL designs against various performance queries. Our approach extends hybrid AADL to support the modeling of environment uncertainties. Furthermore, we propose a set of transformation rules that can automatically translate AADL designs together with designers’ requirements into networks of priced timed automata and performance queries, respectively. Comprehensive experimental results on the movement authority scenario of Chinese train control system level 3 demonstrate the effectiveness of our approach.

/pdf/quantitative-performance-evaluation-of-uncertainty-aware-43bd6l7llh.pdf

Quantitative Performance Evaluation of Uncertainty-Aware Hybrid AADL Designs Using Statistical Model Checking

Unified Modeling Language (UML) activity diagrams are widely used in modeling the dynamic aspects of system designs. However, due to frequent interactions between systems and external uncertain environment, the current version of UML activity diagrams cannot be used to accurately capture and quantify the overall timing behaviors of complex systems. To address this issue, this paper extends the UML activity diagrams to enable the stochastic modeling of user inputs and action executions, which strongly affect the overall timing behaviors of systems. Based on the statistical model checker UPPAAL-SMC, this paper proposes an automated framework that can perform quantitative reasoning under various functional and non-functional queries. Experimental results demonstrate the effectiveness of our proposed approach.

/pdf/quantitative-timing-analysis-of-uml-activity-diagrams-using-r3kpd9kwzt.pdf

Quantitative timing analysis of UML activity diagrams using statistical model checking

Since Internet of Things (IoT) applications are deployed within open physical environments, their executions suffer from a wide spectrum of uncertain factors (e.g., network delay, sensor inputs). Although ThingML is a promising IoT modeling and specification language which enables the fast development of resource-constrained IoT applications, it lacks the capability to model such uncertainties and quantify their effects. Consequently, within uncertain environments the quality and performance of IoT applications generated from ThingML designs cannot be guaranteed. To explore the overall runtime performance variations caused by environmental uncertainties, this paper proposes a quantitative uncertainty evaluation framework for ThingML-based IoT designs. By adopting network of priced timed automata as the model of computation and statistical model checking as the evaluation engine, our approach can model uncertainties caused by external environments as well as support various kinds of performance queries on the extended ThingML designs. Experimental results of two comprehensive case studies demonstrate the efficacy of our approach.

Quantitative Analysis of Variation-Aware Internet of Things Designs Using Statistical Model Checking

Aiming at high performance, more and more Cyber-Physical Systems (CPSs) adopt Multiprocessor System-on-Chips (MPSoCs) as computation units. However, due to increasing integration of transistors on a die, the power densities together with performance variations of MPSoC chips have been increasing dramatically. Consequently, the MPSoC-based CPSs might become unsustainable and unreliable. Although various Task Allocation and Scheduling (TAS) heuristics have been proposed to minimize the hotspot time (i.e., duration of thermal emergency) and energy consumption of MPSoC designs, few of them can guarantee the highest performance yield under process variations without violating energy, thermal and timing constraints. To address these challenges, this paper proposes a novel energy- and thermal-aware TAS evaluation and optimization framework. Based on statistical model checking techniques, our approach enables accurate modeling and reasoning of the performance yield of real-time MPSoC designs under joint energy and thermal constraints. To enable system-level design space exploration, we propose a regression analysis-based method that can drastically reduce the overall exploration efforts. Experimental results show that our fully-automated approach can not only allow accurate sustainability-oriented reasoning of TAS solutions under specified thermal and energy constraints, but also enable the quick search of optimal TAS solutions on different MPSoC architectures with the highest performance yield.

/pdf/sustainability-oriented-evaluation-and-optimization-for-2s91agoq4p.pdf

Sustainability-Oriented Evaluation and Optimization for MPSoC Task Allocation and Scheduling under Thermal and Energy Variations

The invention discloses a temperature-aware method for assessing a MPSoC task allocation and scheduling policy under process variation. The method comprises the following steps of: according to MPSoC platform design information and the task allocation and scheduling policy, generating a TAS mapping instance; integrating a power consumption model, a temperature model and MPSoC platform process variation information and performing modeling, transforming the TAS mapping instance into a corresponding executable NPTA model, and at the same time, generating a background configuration to be accessed by each model; transforming a MPSoC design constraint given by a user into an attribute querying statement, randomly simulating the NPTA model, generating and analyzing statistical result data, and assessing whether the current task allocation and scheduling policy satisfies the design constraint; if yes, choosing an optimal solution; and if not, modifying the task allocation mode and the scheduling policy, to find an optimal solution. The method provided by the invention can accurately reflect performance output of a temperature sensitive task allocation and scheduling instance under process variation, so as to help an MPSoC designer to choose an optimal task allocation and scheduling policy during designing.

Temperature-aware method for assessing MPSoC task allocation and scheduling policy under process variation

To maximize the overall performance yield, variation-aware analysis is becoming a key step in Multiprocessor System-on-Chip (MP-SoC) Task Allocation and Scheduling (TAS). Although various approaches have been investigated to improve performance yields, most of them cannot perform quantitative comparison among existing TAS heuristics, which is important for MPSoC designers to make decisions. Based on the statistical model checker UPPAAL-SMC, we propose a framework that can automatically evaluate the performance yield of TAS strategies under time and power constraints with variations. Experimental results show that our approach can not only filter inferior strategies efficiently, but also support the automated tuning of architecture and constraint parameters to achieve the required performance yield.

https://esl.cise.ufl.edu/Publications/date15.pdf

Variation-aware evaluation of MPSoC task allocation and scheduling strategies using statistical model checking

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Variation-aware evaluation of MPSoC task allocation and scheduling strategies using statistical model checking