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An apparatus and method is described herein for conditionally committing /andor speculative checkpointing transactions, which potentially results in dynamic resizing of transactions. During dynamic optimization of binary code, transactions are inserted to provide memory ordering safeguards, which enables a dynamic optimizer to more aggressively optimize code. And the conditional commit enables efficient execution of the dynamic optimization code, while attempting to prevent transactions from running out of hardware resources. While the speculative checkpoints enable quick and efficient recovery upon abort of a transaction. Processor hardware is adapted to support dynamic resizing of the transactions, such as including decoders that recognize a conditional commit instruction, a speculative checkpoint instruction, or both. And processor hardware is further adapted to perform operations to support conditional commit or speculative checkpointing in response to decoding such instructions.

Apparatus, method, and system for providing a decision mechanism for conditional commits in an atomic region

One embodiment of the invention is a method for producing a hardware solver 502 for intermediate code 503 comprising analyzing intermediate code for at least one instantiation that may cause at least one of wire delay and congestion in the solver, forming compensation 533 for the least one instantiation, and forming the solver 507 in accordance with the compensation.

A system and method for reducing wire delay or congestion during synthesis of hardware solvers

A CDFG which is a graph representing calculations and a data flow included in the design specifications of a circuit is generated S 101, a clock cycle required for the processing is obtained and thus an allocated resource connection graph is generated S 102. When the allocated resource connection graph includes nodes to which hardware resources having the same function are allocated, a sharing edge for controlling sharing of the nodes is added between the nodes S 103. A provisional layout of the allocated resource connection graph having the sharing edge added thereto is provided S 104, and the nodes of the allocated resource connection graph are shared based on the layout result S 105. The sharing edge is provided with attribute or weight such as attraction or repulsion. Thus, the distance between the nodes in the layout result is controlled and the degree at which the resources are shared is controlled.

High level synthesis method for semiconductor integrated circuit

First of all, the number of referencing of a variable described in a behavior level circuit is calculated Next, a bit width of the variable is extracted, and a plurality of memories capable of data transferring of the extracted bit width are selected Next, a sum of a frequency of memory access for each of the selected plurality of memories when the variable is allocated thereto is calculated based on the number of referencing and the bit width of the variable After that, as a target for allocating the variable, a memory that minimizes the calculated sum of the frequency of the memory access is selected

High level synthesis method and high level synthesis apparatus

A high-level synthesis method of the present invention includes: generating a CDFG (Control Data Flow Graph) based an input file describing a behavior of a digital circuit; allocating each node of the CDFG generated in the CDFG generation, expressing contents of processing, to a time synchronized with a clock called a Step, based on the CDFG and a constraint condition of the digital circuit described in a constraint file, thereby scheduling the CDFG; generating allocation information representing how resources for constituting the digital circuit are allocated to respective nodes of the CDFG scheduled in the scheduling, based on resource-level layout information representing a layout of the resources, and circuit information representing a connecting relationship between the resources; and outputting the circuit information generated in the allocation and circuit information generation.

High-level synthesis method

A program optimization device which, when optimizing a program, performs optimization depending on characteristics of data to be processed by the program without having to execute the program before the optimization, includes: an intermediate code conversion unit that converts an input program to be optimized, into an intermediate code; a variable value setting unit that sets a possible value of a variable according to externally provided information; a node value calculation unit that calculates a possible value of a node included in the intermediate code according to the value set by the variable value setting unit; an intermediate code optimization unit that optimizes the intermediate code according to the value calculated by the node value calculation unit; and an output program conversion unit that converts the intermediate code optimized by the intermediate code optimization unit, to an output program.

Program optimization device and program optimization method

A program conversion method that can increase variations of applicable optimizations and effects of the optimization, by being provided with characteristics of a variable or an association between two or more variables as hint information for optimization by a programmer or profiler. The program conversion method converts a source program in a computer and includes: obtaining a constraint equation including at least one of a variable in the source program, a constant, an operator, a pseudo variable, and a built-in function and producing a truth-value; and converting the source program by optimizing the constraint.

Program conversion method using hint information that indicates association between variables

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