The DC design considerations associated with optimizing epitaxial Si- and SiGe-base bipolar transistors for the 77-K environment are examined in detail. Transistors and circuits were fabricated using four different vertical profiles, three with a graded-bandgap SiGe base, and one with a Si base for comparison. All four epitaxial-base profiles yield transistors with DC properties suitable for high-speed logic applications in the 77-K environment. The differences between the low-temperature DC characteristics of Si and SiGe transistors are highlighted both theoretically and experimentally. A performance tradeoff associated with the use of an intrinsic spacer layer to reduce parasitic leakage at low temperatures and the consequent base resistance degradation due to enhanced carrier freeze-out is identified. Evidence that a collector-base heterojunction barrier effect severely degrades the current drive and transconductance of SiGe-base transistors operating at low temperatures is provided. >

On the profile design and optimization of epitaxial Si- and SiGe-base bipolar technology for 77 K applications. I. Transistor DC design considerations

This paper presents an extensive characterization and modeling of a commercial 28-nm FDSOI CMOS process operating down to cryogenic temperatures. The important cryogenic phenomena influencing this technology are discussed. The low-temperature transfer characteristics including body-biasing are modeled over a wide temperature range (room temperature down to 4.2 K) using the design-oriented simplified-EKV model. The trends of the free-carrier mobilities versus temperature in long and short-narrow devices are extracted from dc measurements down to 1.4 K and 4.2 K respectively, using a recently-proposed method based on the output conductance. A cryogenic-temperature-induced mobility degradation is observed on long pMOS, leading to a maximum hole mobility around 77 K. This work sets the stage for preparing industrial design kits with physics-based cryogenic compact models, a prerequisite for the successful co-integration of FDSOI CMOS circuits with silicon qubits operating at deep-cryogenic temperatures.

Characterization and modeling of 28-nm FDSOI CMOS technology down to cryogenic temperatures

For pt.I see ibid., vol.40, no.3, p.525-41 (1993). The circuit performance issues associated with optimizing epitaxial Si- and SiGe-base bipolar technology for the liquid-nitrogen temperature environment are examined in detail. It is conclusively demonstrated that the notion that silicon-based bipolar circuits perform poorly at low temperatures is untrue. Transistor frequency response is examined both theoretically and experimentally, with particular attention given to the differences between SiGe and Si devices as a function of temperature. ECL and NTL ring oscillator circuits were fabricated for each of the four profiles described in pt.I. The minimum ECL gate delay for a SiGe base is essentially unchanged from its room-temperature value. ASTAP models were used to explore circuit operation under typical wire loading. The results indicate that epitaxial-base bipolar technology offers significant leverage for future cryogenic applications. >

On the profile design and optimization of epitaxial Si- and SiGe-base bipolar technology for 77 K applications. II. Circuit performance issues

To study the current‐carrying capability of interconnections between conducting planes in a YBa2Cu3Ox‐insulator multilayer system, the transport properties of laser‐deposited YBa2Cu3Ox striplines at different step edges in 〈100〉 SrTiO3 substrates were investigated. Step edges with various heights between 100 and 800 nm and slope angles a=2.5°, 10°, 25°, 40°, and 65° were fabricated by Ar+ ion milling. The previous ion milling of one part of the substrate does not affect the crystal growth and the transport properties of the superconductor, which has been checked by electrical and x‐ray measurements. Two ways for a high transport current between conducting planes were realized. At flat angles up to 30°, a critical current density of ≳106 A/cm2 at 77 K can be achieved for a step stripline with film thickness d0 smaller than the step height h. If the film thickness d0 is larger than the step height, high superconducting current densities can also be achieved for a≳65°.

Transport properties of epitaxial YBa2Cu3Ox films at step edges

Below approximately 40°K, conventional CMOS technologies show radical departures from room temperature behavior and classical theory, confounding attempts to design readout circuits that have desirable and predictable behavior. Though the effects often seem difficult to explain, they are in all cases due to the effects of carrier freezeout. We have extensively investigated the device properties of CMOS PETs at temperatures very close to absolute zero and conducted a series of process optimizations designed to overcome anomalies that dominate the device behavior. The resulting technology has been used to build readouts for very long wavelength extrinsic silicon detectors, including staring arrays of significant complexity (256x256 pixels). Large die sizes (450 mils) have been produced with high yields (in excess of 50 percent) using this process.

Optimization of cryogenic CMOS processes for sub-10-kelvin applications

A supercomputer using CMOS circuit technology operating at liquid-nitrogen temperatures is discussed. As many as 2000 packaged circuit chips of up to 20000 gates each operate at a temperature below 90 K (which approximately doubles the speed of the circuit chips). Extensive utilization of built-in self-test provides for device and interconnect testability from the wafer at the foundry to the central processor product immersed in nitrogen. The devices are packaged and interconnected with special attention to materials choices to assure reliability of the connection structures. Laboratory cryogenic cycling studies at the device and printed-circuit-board levels are reported. Heat-transfer experiments conducted to validate nucleate boiling peak heat-flux limits of approximately 12 W/cm/sup 2/ in liquid nitrogen are described. A vacuum-jacketed cryostat vessel provides the central processor chips with their liquid-nitrogen environment and allows several thousand signal wires to connect to them with minimal heat leak. A closed-loop cryogenic refrigeration system that recondenses the gaseous nitrogen generated from the boiling heat transfer in the cryostat is described. >

The ETA 10 liquid-nitrogen-cooled supercomputer system

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The ETA 10 liquid-nitrogen-cooled supercomputer system