D. Mantegazza
Intel
20 Papers
179 Citations
D. Mantegazza is an academic researcher from Intel. The author has contributed to research in topics: Phase-change memory & Threshold voltage. The author has an hindex of 12, co-authored 20 publications. Previous affiliations of D. Mantegazza include Polytechnic University of Milan & Micron Technology.
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Papers
Recovery and Drift Dynamics of Resistance and Threshold Voltages in Phase-Change Memories
TL;DR: In this paper, a time-resolved analysis of threshold voltage and resistance in phase-change memory (PCM) is presented, where the authors show that the threshold voltage for electronic switching of the amorphous chalcogenide determines the boundary between programming and readout operation.
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Parasitic reset in the programming transient of PCMs
TL;DR: In this article, the authors studied the programming dynamics in phase change memory cells and found that programming in stand-alone cells is strongly affected by the parasitic capacitance in the measurement setup, leading to a current overshoot after threshold switching of the amorphous chalcogenide.
66
Statistical analysis and modeling of programming and retention in PCM arrays
D. Mantegazza,Daniele Ielmini,Enrico Varesi,Agostino Pirovano,Andrea L. Lacaita +4 more
- 01 Dec 2007
TL;DR: In this article, an analytical, empirical model for set, reset and retention statistics and a physics-based retention model based on crystallization in presence of composition fluctuations at the nm scale of the active material are discussed and modeled.
42
Electrical characterization of anomalous cells in phase change memory arrays
D. Mantegazza,Daniele Ielmini,Agostino Pirovano,B. Gleixner,Andrea L. Lacaita,Enrico Varesi,Fabio Pellizzer,Roberto Bez +7 more
- 01 Dec 2006
TL;DR: New methodologies for PCM failure electrical characterization are discussed, two potential failure mechanisms are discovered, and new approaches for improvements are proposed.
24
Patent
Apparatus and method for drift cancellation in a memory
D. Mantegazza,Prashant S. Damle,Kiran Pangal,Hanmant P. Belgal,Abhinav Pandey +4 more
- 27 Mar 2015
TL;DR: In this paper, a bias logic coupled with at least one memory cell of the plurality, the bias logic is used to apply a first read voltage to the at least single memory cell and then apply a second read voltage on the same memory cell after the first read operation completes.
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