Cheng Chen
Peking University
33 Papers
108 Citations
Cheng Chen is an academic researcher from Peking University. The author has contributed to research in topics: Transistor & MOSFET. The author has an hindex of 10, co-authored 32 publications.
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Papers
Capacitor-less Stochastic Leaky-FeFET Neuron of Both Excitatory and Inhibitory Connections for SNN with Reduced Hardware Cost
Jin Luo,Si Wu,Qianqian Huang,Ru Huang,Liutao Yu,Tianyi Liu,Mengxuan Yang,Zhiyuan Fu,Zhongxin Liang,Liang Chen,Cheng Chen,Liu Shuhan +11 more
- 01 Dec 2019
TL;DR: A capacitor-less neuron based on the novel Leaky-FeFET (L- FeFET) device is proposed and experimentally demonstrated with remarkably reduced hardware cost of only two transistors and one resistor, providing a promising highly-integrated neuron solution for brain-inspired neuromorphic computing system.
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Artificial Neural Network Based on Doped HfO 2 Ferroelectric Capacitors With Multilevel Characteristics
Qilin Zheng,Zongwei Wang,Nanbo Gong,Zhizhen Yu,Cheng Chen,Yimao Cai,Qianqian Huang,Hao Jiang,Qiangfei Xia,Ru Huang +9 more
TL;DR: The performance indicates that more than 78% accuracy and nJ/ms dynamic speed–energy efficiency in recognizing the standard MNIST handwritten digits are achieved, showing the capability of high-density integration and low energy consumption of the capacitive ANNs.
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Comprehensive performance re-assessment of TFETs with a novel design by gate and source engineering from device/circuit perspective
Qianqian Huang,Ru Huang,Chunlei Wu,Zhu Hao,Cheng Chen,Jiaxin Wang,Lingyi Guo,Runsheng Wang,Le Ye,Yangyuan Wang +9 more
- 01 Dec 2014
TL;DR: In this paper, a pocket-mSTFET (PMS-TFET) is proposed and experimentally demonstrated by evaluating the performance from device metrics to circuit implementation for low-power SoC applications.
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A Novel Tunnel FET Design Through Adaptive Bandgap Engineering With Constant Sub-Threshold Slope Over 5 Decades of Current and High $\text{I}_{\mathrm {ON}}/\text{I}_{\mathrm {OFF}}$ Ratio
Yang Zhao,Chunlei Wu,Qianqian Huang,Cheng Chen,Jiadi Zhu,Lingyi Guo,Rundong Jia,Zhu Lv,Yuchao Yang,Ming Li,Ru Huang +10 more
TL;DR: A novel hetero-stacked TFET (HS-TFET) is experimentally demonstrated and optimized for the first time, which can effectively suppress the sub-threshold slope (SS) degradation without leakage current increase through self-adaptively current replenishing with bandgap engineering, greatly alleviating the critical issue of high average SS in conventional TFETs.
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First foundry platform of complementary tunnel-FETs in CMOS baseline technology for ultralow-power IoT applications: Manufacturability, variability and technology roadmap
Qianqian Huang,Rundong Jia,Cheng Chen,Zhu Hao,Lingyi Guo,Junyao Wang,Jiaxin Wang,Chunlei Wu,Runsheng Wang,Weihai Bu,Jing Kang,Wenbo Wang,Hanming Wu,Shiuh-Wuu Lee,Yangyuan Wang,Ru Huang +15 more
- 01 Dec 2015
TL;DR: In this paper, complementary tunnel-FETs (C-TFETs) are integrated with CMOS foundry for high volume production, demonstrating an intrinsic tradeoff between performance enhancement and variability suppression induced by dominant variation source in traditional TFETs.
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