A power efficient and reduced electromagnetic interference (EMI) emissions transmitter for unshielded twisted pair (UTP) data communication applications. Transmit data is processed by a digital filter. The digital filter output data is converted to a current-mode analog waveform by a digital-to-analog converter (DAC). The digital filter is integrated with the DAC binary decoder in a memory device such as a ROM with time multiplexed output. DAC line driver cells are adaptively configurable to operate in either a class-A or a class-B mode depending on the desired operational modality. A discrete-time analog filter is integrated with the DAC line driver to provide additional EMI emissions suppression. An adaptive electronic transmission signal cancellation circuit separates transmit data from receive data in a bidirectional communication system operating in full duplex mode. For a multi-transmitter system, timing circuitry staggers the time base of each transmitter to reduce the aggregate EMI emissions of the multi-transmitter system.

Adaptively configurable class-A/class-B transmit DAC for transceiver emission and power consumption control

Methods and circuitry for implementing monolithic high gain wideband amplifiers. The invention implements an amplifier with a limiter that also performs a signal dividing function. In a specific embodiment, the limiter is designed to make available two in-phase outputs that are then used to drive two gate input lines of a combiner distributed amplifier.

High gain wideband driver amplifier

A method and apparatus for performing frequency detection in an all digital phase lock loop (10). Frequency detection is accomplished using a frequency detector (11), coupled to an digitally controlled oscillator (DCO 16). The frequency detector (11) forces phase alignment of a reference clock signal to the DCO (16) output and then counts the number the DCO (16) output pulses occurring during a reference clock period. The reference clock signal enables the DCO (16) on one signal transition and detects the presence of an oscillator counter (52) output on the same reference clock signal transition, but one reference clock period later. A synchronizer (49) is used to pass the counter (52) output to ensure no metastability. The DCO (16) is then disabled to allow frequency adjustments to occur via other circuitry.

Method and apparatus for performing frequency detection

An amplifier circuit is responsive to an input data signal which is substantially DC balanced. The amplifier circuit is operative to generate an amplified data signal, and includes: a limiting amplifier responsive to the input data signal and to an error correcting signal, the limiting amplifier being operative to generate the amplified data signal; a feed back circuit responsive to a signal proportional to the amplified data signal, the feed back circuit being operative to generate the error correcting signal. The feed back circuit includes: a low pass filter responsive to the signal proportional to the amplified data signal, and operative to generate a filtered signal; and an error amplifier responsive to the filtered signal, and operative to provide the error correcting signal to the limiting amplifier; whereby offset voltage caused by process characteristics of the limiting amplifier, and temperature variations in the limiting amplifier are canceled by the error correcting feedback signal. The limiting amplifier further includes: a first amplifying stage operative to provide a first stage amplified signal; a second amplifying stage responsive to the first stage amplified signal, and operative to provide a second stage amplified signal; and a third amplifying stage responsive to the second stage amplified signal, and operative to generate the amplified data signal. The low pass filter of the feedback circuit generates the filtered signal in response to the second stage amplified signal; and the error correcting signal is provided to the second amplifying stage of the limiting amplifier.

CMOS amplifier providing automatic offset cancellation

Operational amplifier integrated circuits include a differential input stage, a cascode current mirror, a cascode current source and a preferred bias signal generator which is responsive to a clock signal and is electrically coupled to the differential input stage, the cascode current mirror and the cascode current source. This preferred bias signal generator sequentially enables the cascode current mirror and then the differential input stage in response to a rising edge of the clock signal and disables the cascode current mirror and the cascode current source in response to a falling edge of the clock signal. This sequential enablement of the cascode current mirror before the differential input stage improves the unity gain phase margin characteristics of the circuit and the disablement of the cascode current mirror and the cascode current source in response to the falling edge of the clock signal decreases the power consumption requirements of the circuit.

CMOS operational amplifiers having reduced power consumption requirements and improved phase margin characteristics

A cost-effective, low power and low distortion digital data line driver is disclosed with the capability to operate from a limited voltage source while maintaining wide output voltage swings. The line driver has the noise immunity attribute of a fully differential input device without all the usual complex CMFB circuitry normally required. The line driver provides a low distortion output with a low output impedance and maintains its impedance value on the same order of magnitude at frequencies up to four times the Nyquist rate.

Digital data line driver

An all-digital phase-locked loop (ADPLL) is disclosed having a wide bandwidth while maintaining relatively small steps for phase error correction. A random walk filter with memory and a pattern sensitive phase adjustment circuit cooperate to control the ADPLL frequency/phase adjustment rate by taking multiple, relatively smnall steps in phase error correction at fixed intervals of time. A short cycle occurs when the phase disparity is large, interrupting the execution of the fixed interval cycle expediting the ADPLL phase lock time without sacrificing resolution in the phase error correction steps.

Phase-locked loop with pattern controlled bandwidth circuit

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Digital data line driver

Phase-locked loop with pattern controlled bandwidth circuit