This paper is a review of the remarkable progress that has been made during the past few decades in design, modeling, and fabrication of micromachined resonators. Although micro-resonators have come a long way since their early days of development, they are yet to fulfill the rightful vision of their pervasive use across a wide variety of applications. This is partially due to the complexities associated with the physics that limit their performance, the intricacies involved in the processes that are used in their manufacturing, and the trade-offs in using different transduction mechanisms for their implementation. This work is intended to offer a brief introduction to all such details with references to the most influential contributions in the field for those interested in a deeper understanding of the material.

Micromachined Resonators: A Review

Closed-loop neuromodulation is an essential function in future neural implants for delivering efficient and effective therapy. However, a closed-loop system requires the neural-recording front-end to handle large stimulation artifacts—a feature not supported by most state-of-the-art designs. In this paper, we present a neural-recording front-end that has an input range of ±50 mV and can be used in closed-loop systems. The proposed front-end avoids the saturation due to stimulation artifacts by employing a voltage-controlled oscillator (VCO) to directly convert the input signal into the frequency domain. The VCO nonlinearity is corrected using area-efficient foreground polynomial correction. Implemented in a 40-nm CMOS process, the design occupies 0.135 mm $^{\mathrm { {2}}}$ with an analog power of 3 $\mu \text{W}$ and a digital switching power of 4 $\mu \text{W}$ . It achieves ten times higher linear input range than prior art, and 79-dB spurious-free dynamic range at peak input, with an input-referred noise of 5.2 $\mu \text{V}_{\mathrm { {rms}}}$ across the local-field-potential band of 1–200 Hz. With on-chip subhertz high-pass filters realized by duty-cycled resistors, the front-end also eliminates the need of off-chip dc-blocking capacitors.

A ±50-mV Linear-Input-Range VCO-Based Neural-Recording Front-End With Digital Nonlinearity Correction

Clock synchronization is a prerequisite for the realization of emerging applications in various domains such as industrial automation and the intelligent power grid. This paper surveys the standardized protocols and technologies for providing synchronization of devices connected by packet-switched networks. A review of synchronization impairments and the state-of-the-art mechanisms to improve the synchronization accuracy is then presented. Providing microsecond to sub-microsecond synchronization accuracy under the presence of asymmetric delays in a cost-effective manner is a challenging problem, and still an open issue in many application scenarios. Further, security is of significant importance for systems where timing is critical. The security threats and solutions to protect exchanged synchronization messages are also discussed.

/pdf/a-survey-of-clock-synchronization-over-packet-switched-482sqjvsqc.pdf

A Survey of Clock Synchronization Over Packet-Switched Networks

MEMS-based oscillators offer a silicon-based alternative to quartz-based frequency references. Here, a MEMS-based programmable oscillator is presented which achieves better than ±0.5-ppm frequency stability from -40°C to 85°C and less than 1-ps (rms) integrated phase noise (12 kHz to 20 MHz). A key component of this system is a thermistor-based temperature-to-digital converter (TDC) which enables accurate and low noise compensation of temperature-induced variation of the MEMS resonant frequency. The TDC utilizes several circuit techniques including a high-resolution tunable reference resistor based on a switched-capacitor network and fractional-N frequency division, a switched resistor measurement approach which allows a pulsed bias technique for reduced noise, and a VCO-based quantizer for digitization of the temperature signal. The TDC achieves 0.1-mK (rms) resolution within a 5-Hz bandwidth while consuming only 3.97 mA for all analog and digital circuits at 3.3-V supply in 180-nm CMOS.

A Temperature-to-Digital Converter for a MEMS-Based Programmable Oscillator With $ Frequency Stability and $ Integrated Jitter

This paper will provide an update of SiTime's TCXO technology and benchmark 4G & GPS specifications to show that SiTime's MEMS oscillators are capable of meeting these challenging specifications. This MEMS-based TCXO is able to achieve the following which was considered possible only with quartz oscillators: phase noise of −145dBc/Hz @ 10kHz offset and 19.2MHz carrier, frequency stability of 0.2 ppm over industrial temperature range (−40 to 85°C), Allan deviation of 3e-10 using 1 sec averaging time, and random phase jitter of 0.5ps RMS integrated from 12kHz to 20MHz.

Low jitter and temperature stable MEMS oscillators

MEMS-based oscillators have recently become a topic of interest as integrated alternatives are sought for quartz-based frequency references. When seeking a programmable solution, a key component of such systems is a low power, low area fractional-N synthesizer, which also provides a convenient path for compensating changes in the MEMS resonant frequency with temperature and process. We present several techniques enabling efficient implementation of this synthesizer, including a switched-resistor loop filter topology that avoids a charge pump and boosts effective resistance to save area, a high gain phase detector that lowers the impact of loop filter noise, and a switched capacitor frequency detector that provides initial frequency acquisition. The entire synthesizer with LC VCO occupies less than 0.36sq. mm in 0.18 m CMOS. Chip power consumption is 3.7 mA at 3.3 V supply (20 MHz output, no load).

/pdf/a-low-area-switched-resistor-based-fractional-n-synthesizer-u2ogn98n2f.pdf

A Low Area, Switched-Resistor Based Fractional-N Synthesizer Applied to a MEMS-Based Programmable Oscillator

A MEMS-based clock generator achieves sub-ps jitter in 0.18um CMOS. Key enabling techniques include a 48MHz MEMS oscillator, a reference doubler, a linear XOR-based PFD, a switched-resistor loop filter using accumulation mode NMOS varactors, and native NMOS devices with an RC filter. The overall output at 156.25MHz achieves an integrated phase jitter of 668fs rms over an integration bandwidth of 10kHz–20MHz.

/pdf/a-programmable-mems-based-clock-generator-with-sub-ps-jitter-3ukvviqan6.pdf

A programmable MEMS-based clock generator with sub-ps jitter performance

MEMS resonators have recently emerged as an alternative structure to crystal resonators in providing frequency references which achieve better than 50 ppm accuracy over the industrial temperature range. As illustrated in Fig. 13.1.1, a programmable oscillator utilizing a MEMS resonator is achieved by wire bonding a MEMS resonator die to a CMOS die that contains an oscillator sustaining circuit, temperature sensor, fractional-N synthesizer, and various digital blocks. The output of the sustaining circuit provides a 5 MHz reference frequency to the fractional-N synthesizer, which outputs a higher frequency that can be digitally adjusted with sub-ppm resolution over a ≫10% tuning range. By then sending the fractional-N synthesizer output into a programmable frequency divider (i.e., divide-by-N circuit), any frequency in the range of 1 to 115 MHz can be achieved by proper combination of the fractional-N synthesizer and programmable divider settings.

/pdf/a-low-area-switched-resistor-loop-filter-technique-for-1t0cwh10hu.pdf

A low-area switched-resistor loop-filter technique for fractional-N synthesizers applied to a MEMS-based programmable oscillator

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A Low Area, Switched-Resistor Based Fractional-N Synthesizer Applied to a MEMS-Based Programmable Oscillator

A programmable MEMS-based clock generator with sub-ps jitter performance

A low-area switched-resistor loop-filter technique for fractional-N synthesizers applied to a MEMS-based programmable oscillator