Byung-Jun Min
Samsung
40 Papers
541 Citations
Byung-Jun Min is an academic researcher from Samsung. The author has contributed to research in topics: Semiconductor memory & Signal. The author has an hindex of 13, co-authored 37 publications.
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Papers
Patent
Memory device employing NVRAM and flash memory cells
Byung-Gil Jeon,Byung-Jun Min,Hongsik Jeong +2 more
- 18 Dec 2008
TL;DR: In this paper, a memory device includes a memory cell array including a NAND flash cell portion including a plurality of first columns of serially-connected flash memory cells and a non-volatile random access memory (NVRAM) cell portion, which is arranged such that respective word lines are connected to flash memory and NVRAM cells in each row.
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A 58nm 1.8V 1Gb PRAM with 6.4MB/s program BW
Hoe-ju Chung,Byung-Hoon Jeong,Byung-Jun Min,Young-don Choi,Beak-Hyung Cho,Jun-Ho Shin,Jin-Young Kim,Jung Sunwoo,Joon-Min Park,Qi Wang,Yong-Jun Lee,Sooho Cha,Duk-Min Kwon,Sang-Tae Kim,Sung-Hoon Kim,Yoohwan Rho,Mu-Hui Park,Jaewhan Kim,Ickhyun Song,Sunghyun Jun,Jae-Wook Lee,KiSeung Kim,Ki-won Lim,Won-Ryul Chung,Chang-han Choi,HoGeun Cho,Inchul Shin,Woochul Jun,Seok-Won Hwang,Ki-whan Song,Kwang-Jin Lee,Sang-whan Chang,Woo-Yeong Cho,Jei-Hwan Yoo,Young-Hyun Jun +34 more
- 07 Apr 2011
TL;DR: In this paper, a phase-change random access memory (PRAM) was implemented in a 58nm PRAM process with a low power double-data-rate nonvolatile memory (LPDDR2-N) interface.
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28.7 A 58nm 1.8V 1Gb PRAM with 6.4MB/s Program BW
Hoe-ju Chung,Byung-Hoon Jeong,Byung-Jun Min,Young-don Choi,Beak-Hyung Cho,Jun-Ho Shin,Jin-Young Kim,Jung Sunwoo,Joon-Min Park,Qi Wang,Yong-Jun Lee,Sooho Cha,Duk-Min Kwon,Sang-Tae Kim,Sung-Hoon Kim,Yoohwan Rho,Mu-Hui Park,Jaewhan Kim,Ickhyun Song,Sunghyun Jun,Jae Wook Lee,KiSeung Kim,Ki-won Lim,Won-Ryul Chung,Chang-han Choi,HoGeun Cho,Inchul Shin,Woochul Jun,Seok-Won Hwang,Ki-Whan Song,Kwang-Jin Lee,Sang-whan Chang,Woo-Yeong Cho,Jei-Hwan Yoo,Young-Hyun Jun +34 more
- 01 Jan 2011
TL;DR: This paper presents a PRAM, implemented in a 58nm PRAM process with a low power double-data-rate nonvolatile memory (LPDDR2-N) interface, and shows its promising scalability and low cost process.
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An embedded nonvolatile FRAM with electrical fuse repair scheme and one time programming scheme for high performance smart cards
Byung-Jun Min,Kang-Woon Lee,Han-Ju Lee,So-Ra Kim,Seung-Gyu Oh,Byung-Gil Jeon,Hee-Hyun Yang,Min-Kyu Kim,Sung-Hee Cho,Honsik Cheong,Chilhee Chung,Kinam Kim +11 more
- 18 Sep 2005
TL;DR: An embedded ferroelectric random access memory with an electrical fuse (e-fuse) repair scheme, in which the repair information can be electrically programmed, was successfully developed for a high performance smart card.
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13.4 A 512Gb 3-bit/Cell 3D 6 th -Generation V-NAND Flash Memory with 82MB/s Write Throughput and 1.2Gb/s Interface
Dongku Kang,Min-Su Kim,Jeon Su Chang,Won-Taeck Jung,Joo-Yong Park,Gyosoo Choo,Dongkyo Shim,Anil Kavala,Seung-Bum Kim,Kyung-Min Kang,Ji-Young Lee,Ko Kuihan,HyunWook Park,Byung-Jun Min,Changyeon Yu,Se-won Yun,Nahyun Kim,Yeon-Wook Jung,Sungwhan Seo,Sung-Hoon Kim,Moo Kyung Lee,James C. Kim,Young San Cha,Kwang-won Kim,Youngmin Jo,Hyun-Jin Kim,Young-don Choi,Jindo Byun,Ji-Hyun Park,Kiwon Kim,Kwon Taehong,Young-Sun Min,Chi-Weon Yoon,Youngcho Kim,Donghun Kwak,Eung-Suk Lee,Wook-Ghee Hahn,Ki-Sung Kim,Kyung-min Kim,Euisang Yoon,Won-Tae Kim,Inryoul Lee,Seung-Hyun Moon,Jeong-Don Ihm,Dae Seok Byeon,Ki-whan Song,Sang-joon Hwang,Kye Hyun Kyung +47 more
- 01 Feb 2019
TL;DR: 3D-technology scaling faces several technical challenges, including as the number of WL stacks increases the channel-hole etch process becomes a limit, since the total WL-mold height increases.
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