In digital communication, errors are introduced during the transmission of data from the transmitter to receiver due to noise or environmental interference. Hence, we have to use some kind of error control coding for error detection and error correction. In this paper we are applying error control mechanisms, like hamming code, BCH codes and reed Solomon codes to detect and correct the errors. Thus we are used Hamming code, ReedSolomon and BCH code control techniques to correct the errors. Lastly we are comparing the capability of error correcting those codes .the comparison is based on the strength of error correcting technique.

Comparison of hamming, BCH, and reed Solomon codes for error correction and detecting techniques

Transformation is an art of wavering chattels from one location to the other location or one zone to the other zone or one pattern to the other pattern. Designing any regular or irregular polygonal structures especially in tile pasting plays decisive portrayal of procreation. Tile pasting is a technique of gluing tiles in sequence of specific nature, and subsidize collection of structures to the constructors. The sequence of tile pasting can be analyzed and the best sequential path will be determined using Viterbi Algorithm. The pictorial representation of Viterbi algorithm is the trellis path that hand out more strength to the algorithm which shows the sequential order of tile pasting effectively. This paper will also be initiated to find the renewable energy produced by gluing triangular tiles of different polygonal structures and gives an intention to identify the most effective structure among the shapes discussed. 

/pdf/an-analysis-on-potential-renewable-energy-system-using-1875tr4t.pdf

An analysis on potential renewable energy system using triangular tile pasting as a Markov Chain in terms of Maximal Clique

A Viterbi decoder system comprises a convolutional encoder and Viterbi decoder. In general, the code words generated from the input series of convolutional encoder arrive at the decoder through a noisy channel; however, the channel noise can cause corruption of code words. The Viterbi decoder extracts the original input message from the corrupted data using the Viterbi algorithm based on the maximum likelihood principle. A Viterbi decoder mainly comprises four essential units: a branch metrics unit, add-compare-select unit, path metrics unit, and survivor-path memory unit. Related complex calculations are repeated in these units at each clock cycle. In this study, a power- and area-efficient Viterbi decoder architecture that also reduces the computational complexity is proposed. Initially, a hard-decision Viterbi decoder system architecture design for Very Large Scale Integration (VLSI) realization was fulfilled without any further improvement to compare the performance of fundamental and improved designs with respect to power consumption. The initial design constitutes an essential base for the improved power- and area-efficient Viterbi decoder architecture. The improvements were made to achieve the less complex and power-efficient architectural system design. The performance of the proposed architecture was tested by a fieldprogrammable gate array (FPGA) platform, and the results have been reported. The architectural design is described using the Verilog hardware description language for comparing the related tests and performance of FPGA platform.

/pdf/power-efficient-viterbi-decoder-architecture-and-field-46gartlw2q.pdf

Power-Efficient Viterbi Decoder Architecture and Field Programmeble Gate Arrays Fpga Implementation

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Power-Efficient Viterbi Decoder Architecture and Field Programmeble Gate Arrays Fpga Implementation