Thermomechanical fatigue tests were performed on two near-eutectic Sn-Pb solder alloys, 60 Sn-40 Pb and 62 Sn-36 Pb-2 Ag, to examine the effect silver additions have on solder joints. The cyclic load was found to have consistent trends between the two silver alloys (for given amounts of total strain and strain rates). It was found that a decreasing strain rate increased the life of both alloys equally in thermomechanical fatigue. At slower strain rates, the dislocation substructure recovers faster than it work-hardens, which tends to minimize subsequent recrystallization and heterogeneous coarsening of the solder joint. The microstructure of 62 Sn-36 Pb-2 Ag contained large whisker-like Ag/sub 3/Sn precipitates that nucleate and grow out from the Cu/sub 6/Sn/sub 5/ interfacial intermetallics. At this size, the Ag/sub 3/Sn precipitates have little effect on the deformation behavior of the solder. The intermetallics are not detrimental in that they do not prematurely crack, nor are they beneficial because they are too large to stabilize the microstructure. It does not appear, from a microstructural viewpoint, that adding silver to near-eutectic Sn-Pb has any significant effect on improving the thermomechanical fatigue behavior. >

Microstructural evolution during thermomechanical fatigue of 62 Sn-36 Pb-2 Ag and 60 Sn-40 Pb solder joints

In this study, the characteristics of a photovoltaic (PV) ribbon (t = 0.25 mm) joint with 60Sn40Pb and 62Sn2Ag36Pb solders were evaluated using thermal shock tests. The thermal shock tests were performed under three conditions: −40–65 °C, −40–85 °C, and −40–105 °C. The results of these tests were analyzed using electroluminescence (EL) and cross-sectional images. Following testing, broken metal fingers (MFs) were confirmed near the solder joint. PV module degradation was attributed to the broken finger ratio (BFR) based on quantitative analysis of the dark rectangular (DR) regions on the EL images. In addition, the activation energy of the broken MFs was calculated from the increasing BFR. Thermal characteristic variations due to the added Ag in the PV ribbon solder joints were evaluated through observation of solder micro-structure changes following thermal shock tests.

Comparison of the 60Sn40Pb and 62Sn2Ag36Pb Solders for a PV Ribbon Joint in Photovoltaic Modules Using the Thermal Shock Test

Reliability testing: Bibliography

PL programs have made signifi cant and continuous use of electronics technology from the very beginning. In fact, the VT fuze was a marvel of the Laboratory’s electronics technology and the ingenuity of its practitioners. Electronics technology at APL can be subdivided into fi ve broad areas: microelectronics and advanced packaging, RF and microwaves, embedded computers and programmable devices, microelectromechanical systems, and optoelectronics/photonics. In each area, a historical background is presented along with the status of current activities and the trends, directions, and challenges for evolution at the Laboratory. This information was compiled from the APL Senior Leadership Team Technology Review on Electronics Technology. The Laboratory has developed extensive and, in some cases, unique capabilities and facilities for electronics design, fabrication, testing, and qualifi cation. These assets exist in seven APL departments and have been applied across all program areas. The article also highlights a few of the many electronics technology–intensive projects completed recently or currently under development.

Electronics Technology at APL

The current state-of-the-art regarding LCCs is reviewed in terms of published papers concerning LCC applications, device reliability and attachment techniques. Reliability uncertainties relating to environment, size and attachment geometry are identified. An extensive bibliography is included.

(LCCs) R & M Implications of leadless chip carriers

The results of an extensive program for the solder reflow attachment and reliability testiny of ceramic chip carriers for use in space satellites, implantable biomedical electronics, and underwater instrumentation are discussed in detail. The program was divided in three major parts; 1) the packaging of integrated circuit chips in ceramic carriers; 2) the selection and qualification of solders, reflow methods and cleaning processes; and 3) the validation of the chip carrier-substrate system for high reliability applications. Military Standard environmental testing of ceramic chip carriers alone and carriers attached to thin film and thick film (multilayer) ceramic substrates, glass, sapphire, and various printed wire circuit boards has been conducted. Test results are presented for various carrier-substrate-solder combinations along with discussions of associated failure modes and fabrication problem areas.

The Reflow Attachment and Reliability Testing of Ceramic Chip Carriers

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The Reflow Attachment and Reliability Testing of Ceramic Chip Carriers