PURPOSE:To reduce the unreasonable stand-by time of each processor by controlling the suppressing timing of each bus access when both processors work at one time in a dual processor system. CONSTITUTION:In a dual processor system, two processors 31 and 34 having the bus sequences of different lengths have the independent or simultaneous accesses to a system bus 33. If a bus master except both processors 31 and 34 has a bus access request to the dual processor system, the bus accesses of both processors are discontinued and the bus master is allowed to have a bus access through a bus control operation of the dual processor system. In this case, the bus access is suppressed to the processor 34 having the longer bus sequence and then the bus access of the processor 31 of the shorter bus sequence is suppressed in the prescribed timing. Thus it is possible to minimize the unreasonable stand-by time for both processors despite the suppression applied to the bus accesses of both processors.

Bus control system for dual processor

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Bus control system for dual processor