In this paper, lateral gate-all-around nano-sheet transistors (NSH-FETs) are explored from intrinsic performance to dc and ring oscillator (RO) benchmark compared with FinFETs and nanowire transistors (NW-FETs) for sub-7-nm node. The band structure calculated technology computer aided design results show comparable intrinsic performance to FinFETs at same channel cross section. On top of that, dc and RO are evaluated by taking into account electrostatics, parasitic components, and layout configurations. The NSH-FETs show an advantage in drive current with the NSH width but their RO performance is limited by the device capacitance. The multiple narrow NSH-FET shows ~5% higher drive current compared to the NW-FET at similar subthreshold swing, allowing heavier capacitive loaded circuit. In addition, NSH-FETs can provide the device design freedom from aggressive fin pitch scaling.

Device Exploration of NanoSheet Transistors for Sub-7-nm Technology Node

To address the abating performance improvements from device scaling, innovative 2.5-D and 3-D integrated circuits with vertical interconnects called through-silicon vias (TSVs) have been widely explored. This paper reviews TSVs with focus on the following: 1) key drivers for TSV-based integration; 2) TSV fabrication techniques; 3) TSV electrical and thermomechanical performance fundamentals and characterization techniques; and 4) novel technologies to attain enhanced performance beyond the state-of-the-art TSVs.

Through-Silicon Vias: Drivers, Performance, and Innovations

Silicon (Si) and Germanium (Ge) ultrathin body junctionless field-effect transistor (UTB-JLFET) with $L_{G}= 1$ nm and $L_{G} = 3$ nm were demonstrated by solving the coupled drift-diffusion and density-gradient model. The simulation results show that the Si and Ge channel can be used in ultrashort channel device as long as UTB is employed. As UTB is employed, ultra-short channel device does not need to follow an empirical rule of $T_{\rm ch} = \textrm {L}_{G}/3$ . Furthermore, Ge UTB-JLFET 6T-SRAM cell has reasonable static noise margin value of 149 mV. The circuit performances reveal that UTB-JLFET can be used for sub-5-nm CMOS technology nodes.

Performance Evaluation of Silicon and Germanium Ultrathin Body (1 nm) Junctionless Field-Effect Transistor With Ultrashort Gate Length (1 nm and 3 nm)

For sub-7-nm technology nodes, the gate-all-around (GAA) nanowire-based device structure is a strong candidate to sustain scaling according to Moore’s Law For the first time, the performance of two GAA device options—lateral FET (LFET) and vertical FET (VFET)—is benchmarked and analyzed at the system level using an ARM core processor, based on realistic compact device models at the 5-nm technology node Tradeoffs among energy, frequency, leakage, and area are evaluated by a multi- $V_{\rm th}$ optimization flow A variety of relevant device configurations, including various number of fins, nanowires, and nanowire stacks, are explored The results demonstrate that an LFET GAA core has a larger maximum frequency than its VFET counterpart because the channel stress that can be created in the LFETs results in a larger ON current For fast timing targets, the LFET cores are therefore superior However, for slow timing targets (eg, 5 ns), the VFET cores with three nanowires offer a 7% area reduction and a 20% energy saving compared with the LFET cores with 2fin/2stack at the same leakage power

Technology/System Codesign and Benchmarking for Lateral and Vertical GAA Nanowire FETs at 5-nm Technology Node

In this letter, we have studied the impact on lateral nanowire transistor’s (LNW) performance of reducing the wire diameter from 7 nm to 5 nm. As technology scaling continues, the LNW device size is scaled here for beyond 7-nm nodes. Reducing the NW’s gate length causes huge degradation in electrostatic control of the device. The degraded electrostatic is improved by reducing the wire diameter. DC and ring oscillator benchmark have been performed for different NW size for sub-7-nm node using TCAD-based compact models. Using the 5-nm-diameter-based LNW at the gate length of 10 nm around 8-mV/decade subthreshold slope improvement is observed as compared with the 7-nm-diameter LNW. This leads to the possibility of improved performances for the 5-nm-diameter-based device. The NW device, with 5-nm wire diameter and 10-nm gate length can provide some area gain. Although the 5-nm-diameter device increases channel confinement, due to the reduced drive current and increased parasitics, overall device speed is lagging behind the 7-nm diameter device.

Limitations on Lateral Nanowire Scaling Beyond 7-nm Node

We report for the first time the impact of 3D IC process induced local thermo-mechanical stress effects on CMOS devices for 7nm technology node (N7) operating in the ballistic regime. We show that the ballistic current is less affected by the uniaxial stress than the drift current. The ballistic current ratio decreases for longer gate, it is 80%, 45% of the total current for respectively 14nm and 40nm gate lengths devices resulting in larger TSV proximity effects for longer devices. 4 point bending measurements for Ge channel p-FinFETs, confirm the simulated stress sensitivities used to provide a physical estimation of the Keep Out Zone (KOZ). For high mobility channel devices, whereas N7 p-FinFETs exhibits similar TSV stress sensitivities, the KOZ for n-FinFETs is a function of the channel material choice for the co-integration. Unstrained Ge n-FinFETs are largely affected by the TSV proximity, 40% more than Si, SiGe and strained Ge n-FinFETs. Materials like Ge and InGaAs have a reduced sensitivity to the vertical stress component whereas the impact is significant in the case of Si and SiGe n-type devices, with more than 10% change in drive current for 400MPa compressive vertical stress.

Impact of 3D integration on 7nm high mobility channel devices operating in the ballistic regime

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Impact of 3D integration on 7nm high mobility channel devices operating in the ballistic regime