Zero suppression

Abstract: ULTIMATE is a reticle size CMOS Pixel Sensor (CPS) designed to meet the requirements of the STAR pixel detector (PXL). It includes a pixel array of 928 rows and 960 columns with a 20.7 μm pixel pitch, providing a sensitive area of ~ 3.8 cm2. Based on the sensor designed for the EUDET beam telescope, the device is a binary output sensor with integrated zero suppression circuitry featuring a 320 Mbps data throughput capability. It was fabricated in a 0.35 μm OPTO process early in 2011. The design and preliminary test results, including charged particle detection performances measured at the CERN-SPS, are presented.

Abstract: CMOS Monolithic Active Pixel Sensors (MAPS) have demonstrated their strong potential for tracking devices, particularly for flavour tagging. They are foreseen to equip several vertex detectors and beam telescopes. Most applications require high read-out speed, which imposes sensors to feature digital output with integrated zero suppression. The most recent development of MAPS at IPHC and IRFU addressing this issue will be reviewed. The design architecture, combining pixel array, column-level discriminators and zero suppression circuits, will be presented. Each pixel features a preamplifier and a correlated double sampling (CDS) micro-circuit reducing the temporal and fixed pattern noises. The sensor is fully programmable and can be monitored. It will equip experimental apparatus starting data taking in 2009/2010.

Abstract: In this paper we present the front end electronics for the time projection chamber (TPC) of the ALICE experiment. The system, which consists of about 570000 channels, is based on two basic units: (a) an analogue ASIC (PASA) that incorporates the shaping-amplifier circuits for 16 channels; (b) a mixed-signal ASIC (ALTRO) that integrates 16 channels, each consisting of a 10-bit 25-MSPS ADC, the baseline subtraction, tail cancellation filter, zero suppression and multi-event buffer. The complete readout chain is contained in front end cards (FEC), with 128 channels each, connected to the detector by means of capton cables. A number of FECs (up to 25) are controlled by a readout control unit (RCU), which interfaces the FECs to the data acquisition (DAQ), the trigger, and the detector control system (DCS). A function of the final electronics (1024 channels) has been characterized in a test that incorporates a prototype of the ALICE TPC as well as many other components of the final set-up. The tests show that the system meets all design requirements. Originally conceived and optimized for the time projection chamber (TPC) of the ALICE experiment, its architecture and programmability make this system suitable for the readout of a wider class of detectors.

Abstract: A PC based high speed silicon microstrip beam telescope consisting of several independent modules is presented. Every module contains an AC-coupled double sided silicon microstrip sensor and a complete set of analog and digital signal processing electronics. A digital bus connects the modules with the data acquisition (DAQ) PC. A trigger logic unit coordinates the operation of all modules of the telescope. The system architecture allows easy integration of any kind of device under test into the DAQ chain. Signal digitization, pedestal correction, hit detection and zero suppression are done by hardware inside the modules, so that the amount of data per event is reduced by a factor of 80 compared to conventional readout systems. In combination with a two level DAQ scheme, this allows event rates up to 7.6 kHz . This is a factor of 40 faster than conventional VME based beam telescopes while comparable analog performance is maintained, achieving signal to noise ratios of up to 70:1. The telescope has been tested in the SPS testbeam at CERN. It has been adopted as the reference instrument for testbeam studies for the ATLAS pixel detector development.