Zero instruction set computer

Abstract: Implementation of the new IBM Zero Instruction Set Computer (ZISC036) on a PC/ISA-bus card as well as on a VME-card is reported The ZISC circuit has 36 processing elements of a type similar to that of Radial Basis Function (RBF) neurons It is a highly parallel and cascadable building block with on-chip learning capability, and is well suited for pattern recognition, signal processing, etc Results of a test on identification of simulated Higgs events are given

Abstract: The last generation of infrared imaging aircraft seekers and trackers uses pattern recognition algorithms to find and keep a lock on an aircraft in the presence of decoy flares. These algorithms identify targets, based on the features of the various objects in the missile’s field of view. Because modern both aircrafts and missiles fly faster than sound, speed of operation of the target identifier is critical. In this article, we propose a target recognition system that respects this time constraint. It is based on an artificial neural network implemented in hardware, as a set of parallel processors on a commercially available silicon chip called a ZISC, for zero instruction set computer. This chip would be integrated in the infrared missile seeker and tracker. We describe the characteristics of the images that the image processing module of this seeker and tracker extracts from the infrared video frames and show how to construct from these translation and rotation invariant features that can be used as input to the neural network. We determine the individual discriminating power of these features by constructing their histograms, which allows us to eliminate some as not being useful for our purpose. Finally, by testing our system on real data, we show that it has a 90% success rate in aircraft-flare identification, and a processing time that during this time, the aircrafts and missiles will have traveled only a few millimeters. Most of the images on which the neural network makes its mistakes are seen to be hard to recognize even by a human expert.

Abstract: The new IBM Zero Instruction Set Computer (ZISC) provides a radial basis function neural network The first generation chip (ZISC036) allows for 64 8-bit inputs, 36 RBF neurons in the middle layer, and up to 16383 possible output categories Forward processing takes 4μs with a 20MHz clock Cascading multiple chips increases the number of available RBF’s with no increase in processing time The chip also executes a learning algorithm We report on tests of the ZISC with a high energy physics related task

Abstract: Most of applications on neural adaptive process control are developed on back-propagation or CMAC algorithms. We present here a new approach based on a derivative of Radial Basis Function Network: The Restricted Coulomb Energy (RCE) for a parallel implementation of adaptive process control. The RCE network has been implemented on a single board based on the Zero Instruction Set Computer (ZISC-036) neural processor of IBM. The network learning consists on identification of a real second order process (DC motor with position sensor). We expose the learning and generalization phases of network, then we give simulation and experimental results.