Zero flag

Abstract: A portable electronic device of this invention has a control CPU (Central Processing Unit) and a data memory. The data memory is divided into a plurality of areas, and each area consists of a data area and an attribute area indicating an attribute of the data area. The attribute area consists of a first flag indicating whether or not data is stored in the data area, a second flag indicating whether or not data written in the data area is valid, and a third flag indicating whether or not data written in the data area is stored as a block. When an instruction supplied from a host system is a valid-data rearrangement instruction, the control CPU refers to the second flag, and sets a first flag of a data area whose second flag indicates that data is invalid to indicate that data is unwritten, thus rear-ranging valid data of the data memory so that no invalid data area is present between valid data areas. When the third flag indicates write incompletion, the control CPU sets the second flag to make the data area invalid.

Abstract: A superscalar microprocessor is provided with a reorder buffer for storing the speculative state of the microprocessor and a register file for storing the real state of the microprocessor. A flags register stores the real state of flags that are updated by flag modifying instructions which are executed by the functional units of the microprocessor. To enhance the performance of the microprocessor with respect to conditional branching instructions, the reorder buffer includes a flag storage area for storing flags that are updated by flag modifying instructions. The flags are renamed to make possible the earlier execution of branch instructions which depend on flag modifying instructions. If a flag is not yet determined, then a flag tag is associated with the flag storage area in place of that flag until the actual flag value is determined. A flag operand bus and a flag tag bus are provided between the flag storage area and the branching functional unit so that the requested flag or flag tags are provided to instructions which are executed in the branching functional unit.

Abstract: A technique and implementation of generating and supplying synchronization and error checking signals to a serially transmitted data stream includes the generation of flag bytes which define the end boundaries of the serial data stream, an abort character for aborting the transmission of a frame of data in response to certain conditions, and a diagnostic evaluation character inserted into the data stream. In addition, the invention provides a technique for ensuring that the unique binary code by which a flag byte is defined occurs in the transmitted data stream only where intended. The flag code has been chosen to contain a prescribed number of consecutive one bits, (i.e. -- six) flanked by zeroes, and circuitry monitors the contents of a data frame as it is being serialized out for transmission to a remote terminal at times other than during flag transmission. When five consecutive one bits are detected, serializing out of the next bit in the data is interrupted, and a dummy zero bit is inserted prior to the next bit. As a result, the transmitted frame of data will contain no more than five consecutive one bits, except during the flag bytes, (or an abort character) thus ensuring proper synchronization of the end points of the frame. At the receiver terminal, detection and decoding circuitry also monitors the number of consecutive one's in the received data stream. When five consecutive one's are detected, the receiver decoder circuitry checks to see whether the next bit is a dummy zero bit. If the next bit is a zero bit, it is deleted so that the intended data will be correctly reassembled.

Abstract: A processor according to the present invention includes a decoding unit 20, an operation unit 40 and others. When the decoding unit 20 decodes Instruction vcchk, the operation unit 40 and the like judges whether vector condition flags VC0∼VC3 (110) of a condition flag register (CFR) 32 are all zero or not, and ( i ) sets condition flags C4 and C5 of the condition flag register (CFR) 32 to 1 and 0, respectively, when all of the vector condition flags VC0∼VC3 are zero, and ( ii ) sets the condition flags C4 and C5 to 0 and 1, respectively, when not all the vector condition flags are zero. Then, the vector condition flags VC0∼VC3 are stored in the condition flags C0∼C3.