Topic
Z-RAM
About: Z-RAM is a research topic. Over the lifetime, 14 publications have been published within this topic receiving 544 citations. The topic is also known as: Z-RAM.
Papers
Proceedings Article•
1 Jun 2006TL;DR: In this article, the operating characteristics and retention times of floating body cells and arrays using Z-RAMreg technology fabricated on a 50 nm DRAM process are presented for the first time, data retention time longer than 8 s at 93degC and 1.6 V wide programming window.
Abstract: The operating characteristics and retention times of floating body cells and arrays using Z-RAMreg technology fabricated on a 50 nm DRAM process are presented. For the first time, data retention time longer than 8 s at 93degC and 1.6 V wide programming window are obtained on floating body cells as small as 54 nm times 54 nm. These results demonstrate the suitability of floating body memories for DRAM applications. These improvements were obtained through optimization of DRAM technology such as junction engineering, thermal treatments, and improved passivation processes.
61 citations
24 Oct 2008
TL;DR: In this article, the leakage current of SOI-based floating body memory (FBM) has been modeled taking into account oxide/SOI interface traps (Dit) and electric field enhanced (EFE) generation of electron hole pairs (EHPs) from trap states via the Poole-Frenkel Effect (PFE).
Abstract: The leakage current of SOI based Floating Body Memory (FBM) has been modeled. The model takes into account oxide/SOI interface traps (Dit) and Electric Field Enhanced (EFE) generation of electron hole pairs (EHPs) from trap states via the Poole-Frenkel Effect (PFE). This model has been used to improve the retention time of Z-RAM by a reduction of both Dit and electric field. It can also be extended to SOI based low power devices.
47 citations
1 Oct 2006
TL;DR: The zero-capacitor (Z-RAMreg) floating body memory is a dynamic memory built on an SOI substrate as mentioned in this paper, which does not rely on an external capacitor to store charge and reading is done by sensing cell current.
Abstract: The zero-capacitor (Z-RAMreg) floating body memory is a dynamic memory built on an SOI substrate. It differs from a DRAM cell in that it does not rely on an external capacitor to store charge and reading is done by sensing cell current. The Z-RAM memory cell stores charge in its floating body and uses this charge to alter the threshold voltage and gain of the cell transistor. The advantages of the Z-RAM cell are numerous and include a smaller cell size, lithographic friendly processing, fast access time, and no additional processing steps for use as an embedded memory (Okhonin et al., 2001). However, there is little published data on the soft error rates (SER) of this type of memory. This paper summarizes the results of accelerated alpha particle testing conducted on four, 1 Mbit Z-RAM test vehicles. As expected from the nature of the Z-RAM operation and its small cell size, its SER was observed to be significantly better than SRAM and comparable to the SER performance of embedded DRAM
46 citations
6 Nov 2009
TL;DR: In this article, the performance of zero capacitor RAM (Z-RAM) devices, developed in a 45nm SOI CMOS technology, is compared with both symmetric and asymmetric doping schemes.
Abstract: In this paper, the performance of Zero capacitor RAM (Z-RAM ® ) devices, developed in a 45nm SOI CMOS technology, is compared with both symmetric and asymmetric doping schemes. It is shown that the asymmetrically doped Z-RAM (AD) devices offer much better memory performance compared to the symmetrically doped Z-RAM (SD) devices.
44 citations
23 Oct 2009
TL;DR: In this article, a SPICE model that predicts the self-sustained operation (SSO) used in programming of a floating body cell (FBC) is presented, which is calibrated to the contributions of the MOS, BJT and Impact Ionization (II) currents, to accurately predict the static and switching characteristics of the cell.
Abstract: A SPICE model that predicts the Self Sustained Operation (SSO) used in programming of a Floating Body Cell (FBC) is presented. This model, which is calibrated to the contributions of the MOS, BJT and Impact Ionization (II) currents, is demonstrated to accurately predict the static and switching characteristics of the cell. Accurate modeling of device capacitances and leakages allow for quantitative estimation of static and dynamic retention of cells in an array, greatly enhancing the ability to model floating body memories.
38 citations
Related Topics (5)
Performance Metrics
| Year | Papers |
|---|---|
| 2011 | 1 |
| 2010 | 3 |
| 2009 | 3 |
| 2008 | 1 |
| 2007 | 3 |
| 2006 | 2 |