XDR DRAM

Abstract: This paper focuses on the design of a 2.4Gbps to 4.8Gbps link developed in TSMC65nmG+ technology, for the high speed and high throughput interface between XDR™ (Extreme data rate) DRAM and ASIC. Applications such as HDTV and high end graphics require high bandwidth interface between controllers and memory. This XDR I/O (XIO) link which is integrated in the controller, interfaces with the XDR™ DRAM and provides the very high per pin bandwidth. To maintain a constant transmit swing the link supports automatic calibration for the on-die termination (ODT) and driver circuit bias. The channel timing between, ASIC pin to XDR-DRAM pin, is calibrated for all the individual pins to de-skew any channel electrical timing differences to align the data transfer during Memory Read and Writes. This calibration is done periodically to maintain constant timing margin throughout the operation. The self biased [1] regulated PLL dual loop architecture based on [2] is used which minimizes the clock jitter and enables high speed operation. A novel programmable Voltage Control Oscillator is used here to work at wide range of frequencies. The cell with 8bit wide data bus and 16bit wide command bus, consumes 520mW at 4.0Gbps.

Abstract: A method, an apparatus, and a computer program product are provided for the handling of write mask operations in an XDR DRAM memory system. This invention eliminates the need for a two-port array because the mask generation is done as the data is received. Less logic is needed for the mask calculation because only 144 of the 256 possible byte values are decoded. The mask value is generated and stored in a mask array. Independently, the write data is stored in a write buffer. The mask value is utilized to generate a write mask command. Once the write mask command is issued, the write data and the mask value are transmitted to a multiplexer. The multiplexer masks the write data using the mask value, so that the masked data can be stored in the XDR DRAMS.