Topic
Wafer testing
About: Wafer testing is a research topic. Over the lifetime, 4052 publications have been published within this topic receiving 64204 citations. The topic is also known as: wafer testing.
Papers published on a yearly basis
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Papers
Patent•
14 Feb 1991
TL;DR: In this article, each transistor or logic unit on an integrated wafer is tested prior to interconnect metallization by specially fabricated flexible tester surface made in one embodiment of several layers of flexible silicon dioxide, each layer containing vias and conductive traces leading to thousands of microscopic metal probe points.
Abstract: Each transistor or logic unit on an integrated wafer (1) is tested prior to interconnect metallization. By means of CAD software, the transistor or logic units placement net list is revised to substitute redundant defect-free logic units for defective ones. Then the interconnect metallization is laid down and patterned under control of a CAD computer syste. Each die in the wafer thus has its own interconnect scheme, although each die is functionally equivalent, and yields are much higher than wich conventional testing at the completed circuit level. The individual transistor or logic unit testing is accomplished by specially fabricated flexible tester surface (10) made in one embodiment of several layers of flexible silicon dioxide, each layer containing vias and conductive traces leading to thousands of microscopic metal probe points (15-1, 15-2) on one side of the test surface (10). The probe points (330) electrically contact the contacts (2-1, 2-2) on the wafer (1) under test by fluid pressure.
321 citations
Patent•
13 Nov 2003TL;DR: A microsystem-on-a-chip (MOS) as mentioned in this paper comprises a bottom wafer of normal thickness and a series of thinned wafers that can be glued and electrically interconnected, and the interconnection layer comprises compliant dielectric material, an interconnect structure, and can include embedded passives.
Abstract: A microsystem-on-a-chip comprises a bottom wafer of normal thickness and a series of thinned wafers can be stacked on the bottom wafer, glued and electrically interconnected. The interconnection layer comprises a compliant dielectric material, an interconnect structure, and can include embedded passives. The stacked wafer technology provides a heterogeneously integrated, ultra-miniaturized, higher performing, robust and cost-effective microsystem package. The highly integrated microsystem package, comprising electronics, sensors, optics, and MEMS, can be miniaturized both in volume and footprint to the size of a bottle-cap or less.
288 citations
Patent•
8 Jun 1998TL;DR: In this article, a method and apparatus for producing schedules for a wafer in a multichamber semiconductor wafer processing tool comprising the steps of providing a trace defining a series of chambers that are visited by a Wafer as the wafer is processed by the tool, initializing a sequence generator with a vertex defining initial wafer positioning within the tool.
Abstract: A method and apparatus for producing schedules for a wafer in a multichamber semiconductor wafer processing tool comprising the steps of providing a trace defining a series of chambers that are visited by a wafer as the wafer is processed by the tool; initializing a sequence generator with a vertex defining initial wafer positioning within the tool; generating all successor vertices to produce a series of vectors interconnecting the vertices that, when taken together produce a cycle that represents a schedule. All the possible schedules are analyzed to determine a schedule that produces the highest throughput of all the schedules.
288 citations
Patent•
24 Oct 1995TL;DR: In this paper, a system for polishing a semiconductor wafer is described, which consists of a platen subassembly defining a polishing area, a slurry supply system delivering slurry to the area, and an optical measurement system measuring film thickness at multiple different locations on the wafer face.
Abstract: A system for polishing a semiconductor wafer, the system comprising a wafer polishing assembly for polishing a face of a semiconductor wafer at a polishing rate and a polishing uniformity, the wafer polishing assembly including a platen subassembly defining a polishing area, a slurry supply system delivering a slurry to the polishing area, and a polishing head selectively supporting a semiconductor wafer and holding a face of the semiconductor wafer in contact with the platen subassembly; and an optical measurement system measuring film thickness at multiple different locations on the wafer face while the wafer is under a liquid, wherein drying of the wafer is avoided while the measurements are taken.
275 citations
Patent•
18 Apr 2001TL;DR: In this paper, a system for polishing a semiconductor wafer is described, which consists of a platen subassembly defining a polishing area, and a head selectively supporting the wafer.
Abstract: A system for polishing a semiconductor wafer, the system comprising a wafer polishing assembly for polishing a face of a semiconductor wafer at a polishing rate and a polishing uniformity, the wafer polishing assembly including a platen subassembly defining a polishing area, and a polishing head selectively supporting a semiconductor wafer and holding a face of the semiconductor wafer in contact with the platen subassembly to polish the wafer face; and a controller selectively adjusting one of a plurality of adjustable polishing parameters during polishing of the wafer.
265 citations
Related Topics (5)
Performance Metrics
| Year | Papers |
|---|---|
| 2025 | 1 |
| 2024 | 4 |
| 2023 | 13 |
| 2022 | 17 |
| 2021 | 16 |
| 2020 | 36 |