Abstract: A battery pack having a plurality of battery pack modules, wherein each battery pack module includes a battery cell and a power converter. The power converters of the plurality of battery pack modules are connected in series to form a string of N battery pack modules such that the voltage across the N battery pack modules defines the output voltage of the battery pack. A controller regulates the output voltage of each battery cell or module power converter and the output voltage of the battery pack by independently controlling each battery cell module in accordance with variables such as state-of-charge (SOC), state-of-health (SOH) and temperature, capacity, and temperature of each individual battery cell module. The power converter may be used to measure impedance of the battery pack by adding a sinusoidal perturbation signal to a reference voltage of the cell battery pack module.

Abstract: This paper presents bandgap reference (BGR) and sub-BGR circuits for nanowatt LSIs. The circuits consist of a nano-ampere current reference circuit, a bipolar transistor, and proportional-to-absolute-temperature (PTAT) voltage generators. The proposed circuits avoid the use of resistors and contain only MOSFETs and one bipolar transistor. Because the sub-BGR circuit divides the output voltage of the bipolar transistor without resistors, it can operate at a sub-1-V supply. The experimental results obtained in the 0.18-μm CMOS process demonstrated that the BGR circuit could generate a reference voltage of 1.09 V and the sub-BGR circuit could generate one of 0.548 V. The power dissipations of the BGR and sub-BGR circuits corresponded to 100 and 52.5 nW.

Abstract: As NAND flash memory continues to scale down to smaller process technology nodes, its reliability and endurance are degrading. One important source of reduced reliability is the phenomenon of program interference: when a flash cell is programmed to a value, the programming operation affects the threshold voltage of not only that cell, but also the other cells surrounding it. This interference potentially causes a surrounding cell to move to a logical state (i.e., a threshold voltage range) that is different from its original state, leading to an error when the cell is read. Understanding, characterizing, and modeling of program interference, i.e., how much the threshold voltage of a cell shifts when another cell is programmed, can enable the design of mechanisms that can effectively and efficiently predict and/or tolerate such errors. In this paper, we provide the first experimental characterization of and a realistic model for program interference in modern MLC NAND flash memory. To this end, we utilize the read-retry mechanism present in some state-of-the-art 2Y-nm (i.e., 20-24nm) flash chips to measure the changes in threshold voltage distributions of cells when a particular cell is programmed. Our results show that the amount of program interference received by a cell depends on 1) the location of the programmed cells, 2) the order in which cells are programmed, and 3) the data values of the cell that is being programmed as well as the cells surrounding it. Based on our experimental characterization, we develop a new model that predicts the amount of program interference as a function of threshold voltage values and changes in neighboring cells. We devise and evaluate one application of this model that adjusts the read reference voltage to the predicted threshold voltage distribution with the goal of minimizing erroneous reads. Our analysis shows that this new technique can reduce the raw flash bit error rate by 64% and thereby improve flash lifetime by 30%. We hope that the understanding and models developed in this paper lead to other error tolerance mechanisms for future flash memories.

Abstract: An essential requirement for a high-performance dual active bridge (DAB) dc-dc converter is to rapidly and accurately maintain its DC output voltage under all operating conditions This paper uses a novel harmonic modeling strategy to create a linearized dynamic model of a DAB that accurately identifies its transient response to both a reference voltage change and an output load-current change Using this model, a feedforward compensation strategy is presented that significantly improves the DAB's transient response to an output load change The transient performance is then further enhanced by analytically compensating for the nonlinear dead-time distortion that is caused by the converter switching processes The resultant control system achieves rapid and precise output voltage regulation for both reference voltage and output load changes The theoretical analysis is confirmed by both matching simulation and experimental investigations

Abstract: LCL-filters are used to mitigate the harmonic current content in grid converters. The LCL-filter resonance must be damped in order to avoid stability problems in the current control. Active damping avoids resistors at the expense of increased control complexity. Large grid impedance variations can challenge the LCL-filter stability. Active damping by using a notch filter on the reference voltage for the modulator is simple to implement and does not require additional sensors. With the notch frequency tuned for the resonant frequency the voltage reference does not contain any component susceptible of exciting the LCL-filter. However, the notch filter tuning requires considerable design effort and the variations in the resonance frequency limit the LCL-filter robustness. This paper proposes a simple tuning procedure for the notch filter that results in proper robustness. In order to cope with the grid inductance variations it is proposed to estimate the resonance frequency by means of Fourier analysis. The Goertzel algorithm, instead of the FFT, is used to reduce the calculation and memory requirements. Thus, the proposed self-commissioning notch filter results robust and consumes little computational resources. Finally, the analysis is validated with both simulation and experiments.

Abstract: In this paper, the load and/or grid connected to an inverter is modeled as the combination of voltage sources and current sources at harmonic frequencies. As a result, the system can be analyzed at each individual frequency, which avoids the difficulty in defining the reactive power for a system with different frequencies because it is now defined at each individual frequency. Moreover, a droop control strategy is developed for systems delivering power to a constant current source, instead of a constant voltage source. This is then applied to develop a harmonic droop controller so that the right amount of harmonic voltage is added to the inverter reference voltage to compensate the harmonic voltage dropped on the output impedance due to the harmonic current. This forces the output voltage at the individual harmonic frequency to be close to zero and improves the total harmonic distortion (THD) of the output voltage considerably. Both simulation and experimental results are provided to demonstrate that the proposed strategy can significantly improve the voltage THD.

Abstract: A simple Vce online monitoring circuit is presented in this paper. It allows an accurate wear out prediction of IGBT modules, in high-power applications, during normal converter operation. Bipolar measurement allows monitoring of both IGBT and antiparallel diode. The circuit uses two serial connected diodes to sense the Vce voltage with millivolt accuracy. One diode acts as a protection to block high DC voltage present on input terminals. When the device is conducting the voltage on the second diode is measured to compensate for the voltage drop on the protection diode thus eliminating voltage offset due to diodes' forward voltage temperature dependency. Using four diodes one can monitor voltages on all power devices in a converter leg.

Abstract: A new scheme for nine-level voltage space-vector generation for medium-voltage induction motor (IM) drives with open-end stator winding is presented in this paper. The proposed nine-level power converter topology consists of two conventional three-phase two-level voltage source inverters powered by isolated dc sources and six floating-capacitor-connected $H$ -bridges. The $H$ -bridge capacitor voltages are effectively maintained at the required asymmetrical levels by employing a space vector modulation (SVPWM) based control strategy. An interesting feature of this topology is its ability to function in five- or three-level mode, in the entire modulation range, at full-power rating, in the event of any failure in the $H$ -bridges. This feature significantly improves the reliability of the proposed drive system. Each leg of the three-phase two-level inverters used in this topology switches only for a half cycle of the reference voltage waveform. Hence, the effective switching frequency is reduced by half, resulting in switching loss reduction in high-voltage devices. The transient as well as the steady-state performance of the proposed nine-level inverter-fed IM drive system is experimentally verified in the entire modulation range including the overmodulation region.

Abstract: A novel energy-efficient V CM -based monotonic capacitor switching scheme for successive approximation register (SAR) analogue to-digital converters (ADCs) is proposed. Based on the third reference voltage V CM and monotonic capacitor switching procedure, the proposed switching scheme achieves 97.66% less switching energy and 75% less number of capacitors over the conventional architecture, resulting in the most energy-efficient switching scheme among the reported switching sequences.

Abstract: In this paper, a 10b 0.5-to-4MS/s asynchronous SAR ADC is proposed and prototyped in 90nm CMOS. The supply voltage is scaled down appropriately (0.4 to 0.7V) for different speeds to minimize power consumption of SAR control and switching energy. Moreover, a charge average switching (CAS) DAC is developed to reduce the switching energy of the DAC without an extra voltage reference and common-mode shift. In near-threshold operation with a scaled-down supply, a double-boosted sample-and-hold (S/H) circuit and a local-boosted switch are implemented for the linearity and accuracy requirements of the 10b ADC.

Abstract: A method of optimizing solid state drive (SSD) soft retry voltages comprises limiting a number of voltage reads and properly spacing and determining the reference voltage at which each voltage is read based on desired Bit Error Rate (BER) and channel throughput. The method determines each reference voltage for a number of soft retry voltage reads based on a hard decision read. The spacing between each read reference voltage is constant since each SSD type requires a number of reads for an accurate presentation of soft retry voltages. The voltage distance between each successive read is limited to a multiple of the constant spacing while the multiple is based on success or failure of the first read. The method determines a limited number of reads, the constant spacing between reads, and a desired reference voltage for each read, thereby increasing valuable throughput of the channel and decreasing BER.

Abstract: This paper proposes a design of ultra-low-power successive approximation register (SAR) analog-to-digital converters (ADC) specially optimized for very low frequency biosensor applications. Two new techniques are introduced: 1) a novel digital-to-analog converter (DAC) switching method suitable for single-ended SAR ADCs; and 2) a counter-based digital control circuitry. The DAC switching method uses VR/2 as an only reference voltage to digitize the input signals within [0, VR ], and reduces the power consumption in the DAC during digitizing by 87.5% versus the traditional one. The counter-based controller can reduce power consumption in the digital circuitry by 30%. Two prototype 8-bit SAR ADCs are designed, one in a TI 0.35-μm Bipolar-CMOS-DMOS (BCD) process and the other in a TSMC 0.18-μm CMOS process. The 0.35-μm ADC consumes 101 nW, and achieves a signal to noise and distortion ratio (SNDR) of 48.2 dB and a figure of merit (FOM) of 227 fJ/conversion-step at 2 kS/s. The 0.18-μm ADC can achieve a SNDR of 46.3 dB with only 27 nW and a FOM of 79.9 fJ/conversion-step at 2 kS/s.

Abstract: An 18-Mb full ternary CAM with low-voltage matchline sensing scheme (LVMLSS) is designed and fabricated in 65-nm bulk CMOS process. LVMLSS has three key techniques: voltage down converter, differential sense amplifier with matchline isolation, and reference voltage generation scheme. With these techniques, LVMLSS can reduce the dynamic power consumption of matchlines to 33% compared with conventional one and realizes 42% fast match-line sensing. At 1.0-V typical supply voltage, 250-MHz search frequency is achieved. The power consumption of fully paralleled search operation at 250 MHz is 9.3 W, which is 66% smaller than previous work. This work has realized high-speed, low-power, and robust large-scale TCAM. We believe that this work will greatly contribute to reducing the power of network systems.

Abstract: Three-stage 18-level hybrid inverter design with novel control method is presented. The inverter consists of main high-, medium-, and low-voltage stages connected in series from the output side. The high-voltage stage is a three-phase, six-switch conventional subinverter. The medium- and low-voltage stages are made of three-level subinverters constructed by H-bridge units. The proposed control strategy assumes a reference input voltage vector and aims to approximate it to the nearest inverter vector. The control concept is based on holding the high-voltage state as long as it is feasible to do so. The reference voltage vector has been represented in a 60°-spaced two axis coordinate system to reduce the computational effort. The concept of the staged-control has been presented, the transformed inverter vectors and their relation to the switching variables have been defined, and the implementation process has been described. The test results verify the effectiveness of the proposed strategy in terms of computational efficiency as well as the capability of the inverter to produce very low distorted voltage with low switching losses.

Abstract: A 10 V programmable Josephson voltage standard has enabled sine waves with voltages up to 7 V RMS to be accurately measured with a differential sampling measurement technique. Expanding the voltage range for this technique enables the direct calibration of the low-frequency ranges of commercial calibrators in the ac voltage mode. This paper reviews the practically achievable performance and challenges of the differential sampling measurement technique that arise when measuring RMS voltages greater than a few volts. A relative Type A uncertainty of 4 parts in $10^{7}$ was achieved with the technique when measuring a 7 V RMS sine wave generated by a calibrator at 62.5 Hz.

Abstract: A switching power supply device includes: a non-linear control type switching control unit that, in accordance with a result of a comparison between a feedback voltage and a reference voltage, performs on/off control of a switch element, and thereby generates an output voltage from an input voltage; a backflow current detection unit that, upon detecting a backflow current flowing to the switch element, forcibly switches off the switch element; and an on-time setting unit that sets an on-time of the switch element, in a case of the backflow current not being detected, in accordance with a duty of the switch element, and in a case of the backflow current being detected, in accordance with a switch voltage appearing at one end of the switch element or the output voltage

Abstract: In future low voltage grids, with multiple inverter interfaced sources connected, voltage regulation may become a necessary task. The potential exists for inverter interfaced sources to be deployed to regulate the voltage at the point of common coupling (PCC) of each inverter interfaced sources. The PCC voltage regulation is attainable with inverter interfaced sources by dynamically controlling the amount of reactive power injected to the power distribution grid by individual systems. In the current research, a closed-loop controller is proposed to regulate the PCC voltage of a solar photovoltaic (PV) system that is connected to a single-phase power distribution feeder (with R to X ratio greater than 1). The plant model of the PCC voltage controller of the PV system is derived considering both reactance and resistance of the network to which the PV system is connected. Three different compensators are evaluated to identify a suitable compensator for the closed-loop PCC voltage controller to regulate the PCC voltage at a given reference voltage. Simulation studies and experimental verification confirm that the theoretical approach taken to derive the control plant model of the PCC voltage controller is accurate and the procedure that is followed to design the controller is robust. The control design procedures illustrated in the current research leads to a PCC voltage control system with acceptable dynamic and steady state performance.

Abstract: In this paper, we present two modulation schemes for generating unbalanced voltages by means of four-leg voltage-source inverters. The first modulation is an extended scheme of a digital-scalar pulsewidth modulation previously proposed for controlling three-leg inverters. The second one is based on the decomposition of the voltage reference signals into their symmetrical components. The schemes are compared theoretically by simulations and experimental results. As a consequence, we find out a total equivalence between the two modulations despite their different conceptions. The fundamentals of both techniques and a mathematical proof of their equivalence are unfolded. Also, the performances of the techniques with respect to the harmonic distortion and power switching loss are discussed. The results show that the techniques are effective.

Abstract: A system and a method provide a photovoltaic system which regenerates the output characteristics of the photovoltaic at different ambient condition with high precision under all environmental conditions. The photovoltaic system includes a photovoltaic array, a buck/boost converter, a DC link capacitor to connect the buck/booster converter to a load/inverter, an adaptive network-based fuzzy inference maximum power point tracking controller, a voltage control loop, a proportional integral controller to maintain the output voltage of the photovoltaic array to the reference voltage by adjusting the duty ratio of buck/boost converter.

Abstract: The increase of power electronic subsystems in more-electrical aircrafts (MEA) brings severe challenges to aircraft power distribution in terms of power quality on board. Active filtering is a viable solution to this problem; however, given the high supply frequency in AC-MEA power networks, effective harmonic compensation using standard converter structures, traditional digital control and reasonable devices switching frequency is a demanding task. A five-level active shunt filter with an enhanced deadbeat current controller is proposed in this paper for a fixed frequency 400 Hz aircraft power grid. The controller shows higher immunity to measurement noise compared with the conventional deadbeat current controller. In order to enhance the system performance when the voltage reference has a high rate of change, a modified pulse width modulation algorithm is proposed. The effective reference tracking of the proposed modulation combined with the employed current control approach is experimentally verified. The proposed controller features a high bandwidth of the current control loop, capable of high frequency harmonic compensation, using a reduced devices switching frequency.

Abstract: The present invention discloses a light emitting diode (LED) lighting device, the object of this invention is to prevent flickers and reduce surge current, and to achieve a compact and high efficient LED lighting device. A solution means includes a rectifier circuit for converting an AC voltage into a rectified voltage, a first capacitor for converting the rectified voltage to a DC link voltage, and a DC-DC converter circuit for converting the DC link voltage to supply power to the LED load, a current setting circuit for outputting a current setting value of the DC-DC converter circuit according to the rectified voltage, a shunt circuit connected between the DC output terminals of the rectifier circuit and at least comprising a serial connection body of an impedance and a switch element, and an LED lighting device for controlling the switching circuit of the switch element in the serial connection body. The invention is characterized in that the switching circuit is to turn on at least one switch element in the serial connection body during the period in which the rectified voltage is lower than a desired reference voltage, and the rectified voltage changes to become higher than the desired reference voltage until a desired period has elapsed.

Abstract: An exemplary method and an apparatus implementing the method for an arrangement having a three-phase, multi-level inverter, an output LCL-filter connecting the inverter to a grid, and a virtual-ground connection between the LCL-filter and the neutral point of the DC-link. The method includes determining a zero-sequence component of an LCL-filter inverter-side current, calculating a zero-sequence damping and balancing voltage term based on the LCL-filter inverter-side current zero-sequence component and voltages over the two halves of the DC-link, and adding the zero-sequence damping and voltage balancing term to the output voltage reference.

Abstract: This paper proposes a variable DC-link reference voltage algorithm for wide range of maximum power point tracking (MPPT) for two-string photovoltaic (PV) systems. A multi-string system, which is a kind of PV system, is widely used due to its many merits (such as the ability to use low rating devices, high MPPT efficiency, and so forth). PV systems can choose their input voltages on the basis of their PV cell connection structure. The PV cell connection structure can be restricted because the input voltage and current affect the PV system design. This reduces the MPPT range under some weather conditions. In the restricted PV connection structure, this algorithm enlarges the MPPT range and minimizes the increment of the total harmonic distortion (THD) by selecting the appropriate DC-link voltage reference which is changed by comparing the sorted input voltage. To verify the proposed algorithm, simulation and experiments are conducted to show the results of the performance for the proposed algorithm.

Abstract: Provided is an over-voltage protection device for a resonant wireless power transmission device. The over-voltage protection device includes an amplifier for amplifying a transmission signal, a resonance signal generator for generating a wireless resonance signal according to the transmission signal amplified by the amplifier, a voltage detector for sensing a voltage of the wireless resonance signal generated by the resonance signal generator, and a controller for monitoring the voltage detected by the voltage detector to determine whether the voltage repetitively increases and decreases with periodicity when the voltage is greater than a reference voltage and controlling the amplifier to decrease an output of the transmission device by a value according to a result of the determination.

Abstract: A voltage compensation type pixel circuit of an AMOLED display device includes a driving transistor serially connected to a light emitting element between high-potential and low-potential power lines to drive the light emitting element in response to a voltage supplied to a first node, a first program transistor for supplying a data voltage of a data line to a second node in response to a scan signal of a scan line, a second program transistor for supplying a reference voltage from a reference voltage supply line to the first node in response to the scan signal of the scan line, a merge transistor for connecting the first and second nodes in response to a merge signal of a merge line, a storage capacitor connected between a third node and the second node interposed between the driving transistor and the light emitting element to store a voltage which corresponds to the data voltage in which the threshold voltage is compensated, and first and second reset transistors for initializing at least two of the first, second, and third nodes to an initialization voltage of an initialization voltage line in response to a reset signal of a reset line.

Abstract: An asynchronous 8× interleaved redundant SAR ADC achieving 8.8GS/s at 35mW and 1V supply is presented. The ADC features pass-gate selection clocking scheme for time-skew minimization and per-channel gain control based on low-power reference voltage buffers. The sub-ADC stacks the capacitive SAR DAC (CDAC) with the reference capacitor to reduce the area and enhance the settling speed. It achieves 38.5dB SNDR and 58fJ/conversion-step with a core chip area of 0.025mm2 in 32nm CMOS SOI technology.

Abstract: Channel information and channel conditions that are determined by an Offline Tracking process are used to determine whether or not an adjustment to the read reference voltage can be avoided altogether without detrimentally affecting performance, or, alternatively, to determine a precision with which a read reference voltage adjustment should be made. If it is determined based on the channel conditions that a read reference voltage adjustment can be avoided altogether, read performance is improved by reducing the probability that a read reference voltage adjustment needs to be made during normal read operations. If it is determined based on the channel conditions that a read reference voltage adjustment needs to be made with a particular precision, the read reference voltage is adjusted with that precision. This latter approach is advantageous in that a determination that the precision with which the adjustments can be made is relatively low leads to fewer adjustments having to be made during normal read operations.

Abstract: This article presents a novel technique for precise measurement of time and charge based solely on FPGA (Field Programmable Gate Array) device and few satellite discrete electronic components used in Positron Emission Tomography (PET). Described approach simplifies electronic circuits, reduces the power consumption, lowers costs, merges front-end electronics with digital electronics and also makes more compact final design. Furthermore, it allows to measure time when analog signals cross a reference voltage at different threshold levels with a very high precision of $\sim$ 10ps (rms) and thus enables sampling of signals in a voltage domain.

Abstract: The invention provides a pixel compensation circuit. The pixel compensation circuit comprises a first switch, a second switch, a third switch, a fourth switch, a fifth switch, a sixth switch, a first capacitor, a second capacitor and an organic light-emitting diode, wherein a first end of the first switch receives data voltage; a second end of the first switch receives a first switch signal; a second end of the second switch receives the first switch signal; a second end and a third end of the third switch are both connected to first voltage; a first end of the fifth switch receives reference voltage; a second end of the fifth switch receives a third switch signal; a second end of the sixth switch receives the third switch signal; a first end of the second capacitor is connected to a second end of the first capacitor; a second end of the second capacitor receives a second switch signal; a first end of the organic light-emitting diode is connected to a first end of the sixth switch; and a second end of the organic light-emitting diode is connected to second voltage. Compared with the prior art, the pixel compensation circuit has the advantages that the threshold value voltage of the switches is compensated before a lightening period, so that the influence of the threshold vale voltage on OLED (Organic Light Emitting Diode) current is eliminated, and stable current output of an OLED in a pixel can be kept.