Abstract: For the converter parallel operation, the current sharing between modules is important for the reliability of the system. Among several current sharing schemes, the droop method needs no interconnection between modules, which implies true redundancy. But the droop method has poor voltage regulation and poor current sharing characteristics. In this paper, a novel droop method is proposed for the converter parallel operation, which adaptively controls the reference voltage of each module. This greatly improves the output voltage regulation and the current sharing of the conventional droop method. The analysis of the proposed method and design procedure are provided and experimental results verify the excellent performance of the proposed method.

Abstract: A dynamic voltage restorer (DVR) is a power-electronic controller that can protect sensitive loads from disturbances in the supply system. In this paper, it is demonstrated that this device can tightly regulate the voltage at the load terminal against imbalance or harmonic in the source side. The behavior of the device is studied through steady-state analysis, and limits to achievable performance are found. This analysis is extended to the study of transient operation where the generation of the reference voltage of the DVR is discussed. Once the reference signals are generated, they are tracked using a switching band scheme. A suitable structure in which the DVR is realized by voltage-source inverters (VSIs) is also discussed. Particular emphasis to the rating of this device is provided. Extensive simulation results are included to illustrate the operating principles of a DVR.

Abstract: A dynamic voltage restorer (DVR) is a power-electronic controller that can protect sensitive loads from disturbances in the supply system. In this paper, it is demonstrated that this device can tightly regulate the voltage at the load terminal against imbalance or harmonic in the source side. The behavior of the device is studied through steady-state analysis, and limits to achievable performance are found. This analysis is extended to the study of transient operation where the generation of the reference voltage of the DVR is discussed. Once the reference signals are generated, they are tracked using a switching band scheme. A suitable structure in which the DVR is realized by voltage-source inverters (VSIs) is also discussed. Particular emphasis to the rating of this device is provided. Extensive simulation results are included to illustrate the operating principles of a DVR.

Abstract: PROBLEM TO BE SOLVED: To make voltage loss small and reduce a load on user-side device for switching on/off between an output terminal and a common terminal, and make current control operation such as overcurrent protection exact and stable, in a semiconductor integrated circuit having an output terminal, a control terminal and a common terminal which switches on/off between the output terminal and the common terminal by the controlled voltage given between the control terminal and the common terminal, detects the current which runs between the output terminal and the common terminal, and executes current control such as overcurrent protection. SOLUTION: A reference voltage VE which is to be the operation reference of current control is generated by making use of the difference in the threshold voltages between the gate and the source of a pair of MOS transistor Q3 and Q4.

Abstract: A feedforward maximum power (MP) point tracking scheme is developed for the interleaved dual boost (IDB) converter fed photovoltaic (PV) system using fuzzy controller. The tracking algorithm changes the duty ratio of the converter such that the solar cell array (SCA) voltage equals the voltage corresponding to the MP point at that solar insolation. This is done by the feedforward loop, which generates an error signal by comparing the instantaneous array voltage and reference voltage. The reference voltage for the feedforward loop, corresponding to the MP point, is obtained by an off-line trained neural network. Experimental data is used for off-line training of the neural network, which employs back-propagation algorithm. The proposed fuzzy feedforward peak power tracking effectiveness is demonstrated through the simulation and experimental results, and compared with the conventional proportional plus integral (PI) controller based system. Finally, a comparative study of interleaved boost and conventional boost converter for the PV applications is given and their suitability is discussed.

Abstract: A content addressable memory (CAM) device that includes a plurality of CAM cells coupled to a match line to affect a voltage of the match line in response to data values of the CAM cells and comparand data being in a predetermined logical relationship, and a match detect circuit coupled to the match line and adapted to differentially compare the voltage of the match line with a fixed reference voltage and, in response, generate an output signal having two or more logical states corresponding to the states of the predetermined logical relationship between the data value and the comparand data.

Abstract: There is provided a semiconductor integrated circuit device wherein functional circuit groups are arranged on a chip in a direction spreads, which aims to enhance layout efficiency and to prevent deterioration of element characteristics A unit wiring region IL1P is constituted outside of a power voltage wiring VCC, a part of a second region BIP and a unit wiring region IL1N is constituted outside of a reference voltage wiring VSS, a part of a second region BIN Within the second wiring regions BIP and BIN, connection wirings 11, 12A, 13, 14 are wired These connection wirings connect between units within the logic circuits CIA11, CIR12 or between the logic circuits CIR11, CIR12 There is only arranged an input/output wiring region IOL1 on a first region A1 located between the power voltage wiring VCC1 and the reference voltage wiring VSS1 Since no unit wiring region exists in the first region A1, width of the first region A1 can be laid-out short Accordingly, connection wiring between PMOS/NMOS transistors can be shortened, areas of an N-type well region NW1 and a P-type well region PW1 can be made small Layout efficiency and circuit characteristic can be enhanced, as a result

Abstract: An N-phase switching voltage regulator includes N current sensing elements (14, 16, 23, 24) which carry respective phase currents. The voltages present at the switch node sides of the sensing elements are summed and presented to an amplifier (28) which also receives the regulator's output voltage, to produce an output which is proportional to the regulator's total output current Iout. The invention also provides a means for direct insertion of total inductor output current information into a regulator's voltage-mode control loop, to provide active voltage positioning (AVP) for the output voltage. A voltage based on total inductor output current is summed with the regulator's reference voltage; this sum and Vout are applied to the voltage control error amplifier (114), the output of which is processed to operate the regulator's switches (100, 102). This enables the regulator's ouput to have a desired droop impedance and to provide AVP of Vout as a function of total filtered inductor output current I?out(fltr)?.

Abstract: A NAND EEPROM having a shielded bit line architecture reduces supply voltage and ground noise resulting from charging or discharging bit lines. The EEPROM has a PMOS pull-up transistor and an NMOS pull down transistor connected to a virtual power node. A control circuit for charging or discharging bit lines controls the gate voltage of the PMOS or NMOS transistor to limit peak current when charging or discharging bit lines via the virtual power node. In particular, the control circuit operates the PMOS or NMOS transistor in a non-saturation mode to limit current. One such control circuit creates a current mirror or applies a reference voltage to control gate voltages. A programming method sets up bit lines by pre-charging unselected bit lines via the PMOS pull-up transistor having controlled gate voltage while latches in the programming circuitry charge or discharge selected bit lines according to respective data bits being stored. Another bit line setup includes two stages. A first stage pre-charges all bit lines via PMOS pull-up, and the second stage uses the latches to discharge or leave charged the selected bit lines depending on respective data bits being stored. The gate voltages of NMOS transistors in the programming circuitry can be controlled to reduce noise caused by discharging selected bit lines through the latches.

Abstract: Three different CMOS dynamic comparator topologies for pipeline A/D converters, resistive divider, differential pair, and charge distribution comparators, are analyzed. The topologies considered are fully differential, i.e. both sensing and reference voltage inputs are balanced, consist only of a single stage, and feature zero DC power dissipation with a built-in threshold adjusting input stage. Test structures of the comparators, fabricated in 0.35-/spl mu/m CMOS process, are measured to determine the offset properties of the compared topologies.

Abstract: A dynamic voltage restorer (DVR) is a power electronic controller that can protect sensitive loads from disturbances in the supply system. This device can tightly regulate the voltage at the load terminal against imbalance or harmonic in the source side. The behavior of the device is studied through steady-state analysis, and limits to achievable performance are found. This analysis is extended to the study of transient operation where the generation of the reference voltage of the DVR is discussed. Once the reference signals are generated, they are tracked using a switching band scheme. A suitable structure in which the DVR is realized by voltage source inverters is also discussed. Particular emphasis on the rating of this device is given. Extensive simulation results are included to illustrate the operating principles of a DVR.

Abstract: PROBLEM TO BE SOLVED: To effectively prevent false read by suppressing the unforeseen voltage change of a bit line caused by the capacity coupling between wiring activated at read and a storage node, etc. SOLUTION: This semiconductor storage device has a read capacitor Q2 which is connected between a voltage supply line VL held with power source voltage or reference voltage and a bit line electrically floated at read and whose gate is connected to a storage node SN, and a cap CAP which is connected between a read word line RWL for changing the potential of the storage node SN by applying voltage at read and the storage node SN. The bit line BL is arranged in the upper layer of the capacitor CAP. The read word line RWL covers the lower electrode 7 of the capacitor and the gate electrode 5r of the read transistor Q2, and the voltage supply line VL is capacitively coupled with the read word line RWL, thereby reducing the potential ripple of the storage node SN.

Abstract: An oximeter has an op-amp with a first input, a second input, and an output, the first input being directly connected to a reference voltage. A switch has an input connected to the output of the op-amp, and has a plurality of switch outputs. A transistor has a control input connected to one of the plurality of outputs, and has a current source terminal and a supply terminal. A diode is connected to the current source terminal of the transistor. The supply terminal of the transistor is connected both to the second input of the op-amp and to a second one of the plurality of switch outputs. The switch is thereby in a feedback loop of the op-amp, effecting a feedback-controlled switch for switching the diode on and off.

Abstract: A DC to DC converter includes a comparator, a driver, and a pair of switches. The comparator compares the output voltage with a reference voltage signal and generates a PWM signal. The driver drives the switches so as to force the output voltage to follow the reference signal. In a multiphase architecture, two or more such converter circuits are incorporated to minimize the output voltage ripple and further reduce the recovery time. In a two-phase architecture, two reference signals are phase-shifted by 180 degrees. In an N-phase architecture, the reference signals are phase-shifted by 360/N degrees.

Abstract: A system for improving the power efficiency of an electronic device includes a threshold voltage selector and a supply voltage selector. The threshold voltage selector selects a value of a threshold voltage for operation of the device in response to a present operating condition of the device. The supply voltage selector selects a value of a supply voltage to be applied to the device in response to the present operating condition of the device. The value of the threshold voltage and the value of the supply voltage control a power consumption of the device.

Abstract: When rechargeable batteries have been discharged to a selected voltage reference level, LED 29 (and/or buzzer BZ) and controller 32 may warn the operator that the rechargable batteries should be recharged. Controller 32 may change the selected reference voltage level based upon use history information concerning the rechargeable batteries. The use history information may, e.g., be stored in EEPROM 52 of battery pack 40 . Thus, the rechargeable batteries can be discharged to different voltage levels before the operator is warned that the rechargeable batteries should be recharged. In addition or in the alternative, switch 36 may be disposed between the rechargeable batteries and a motor (M). Controller 32 may open switch 36 when the detected voltage of the rechargeable batteries drop below the selected reference voltage level (or a derivative of the selected reference voltage level) in order to interrupt the flow of current to the motor (M). Thus, the rechargeable batteries can be prevented from being over-discharged and from developing memory effects, thereby prolonging the usable life of the rechargeable batteries.

Abstract: In an LED unit, all of eight LEDs are connected in series. The voltage of a power supply, that is, a battery of a vehicle, 12 V, is insufficient for the eight LEDs. To cope with this, a boosting circuit is provided within the control unit to boost the voltage to about 16 V which is then applied to the eight LEDs. The front end of the LED unit is connected to a constant-current circuit, and a voltage detection circuit is provided near and connected to this constant-current circuit for detecting the voltage applied to the constant-current circuit. The voltage detected by the voltage detection circuit is compared with a reference voltage drawn from the power supply, is amplified in an amplifier, and is input as a boosting control signal into the boosting circuit. The boosting control signal is output so as to regulate the boosted voltage in such a manner that the voltage detected in the voltage detection circuit is a lowest possible voltage.

Abstract: PROBLEM TO BE SOLVED: To reduce power loss while performing constant-current drive irrespective of the unevenness of characteristics of a light emitting element by automatically regulating a voltage applied to a constant-current driver for driving a plurality of light emitting elements sequence to a necessary amplitude for a constant-current operation. SOLUTION: The lowest voltage of voltages applied to a plurality of constant- current drivers connected with a plurality of light emitting elements sequence is selected as a detecting voltage. The output voltage of a power source circuit is automatically controlled so that the value of the detecting voltage becomes a low voltage (that is, a reference voltage) for constant-current operating the constant-current driver. COPYRIGHT: (C)2004,JPO

Abstract: A method and system for calibrating a time constant within an integrated circuit. A voltage storage element is charged, and the time required to achieve a reference voltage on the storage element is measured. The measured time is compared to a desired time. It necessary, an adjustable impedance is modified to change the charging time, and the cycle may be repeated until the charging time matches the desired time. In this novel manner, an actual RC time constant, as rendered in a particular integrated circuit, is measured and potentially adjusted to match a desired time constant. Advantageously, configuration information of the adjustable impedance may be communicated to other circuitry within the integrated circuit to enable such circuitry to implement the same RC time constant in analog signal processing. Consequently, embodiments of the present invention overcome incidences of wide tolerance in passive components implemented in integrated circuits. Beneficially, no external test equipment is required.

Abstract: A method for providing self-calibration for adaptively adjusting a power supply voltage in a digital processing system is provided that includes providing a nominal power supply voltage to the system as a power supply voltage. A regulator clock signal is propagated through a delay line. The delay line comprises a plurality of delay cells and is operable to function based on the nominal power supply voltage. A plurality of pairs of delay cells are sampled until a first and second delay cell are identified based on the first delay cell receiving the regulator clock signal and the second delay cell failing to receive the regulator clock signal at a specified time. A reference voltage is provided to the system as the power supply voltage. The system is operated using the first and second delay cells to determine whether to adjust the power supply voltage for the system.

Abstract: A method for controlling a residual battery capacity of a secondary battery, by which the precision of the energy management of the system can be improved substantially, is provided. A current flowing through the battery is detected and the detected current is multiplied by a predetermined charge efficiency so that an operation on a residual battery capacity is performed at least by current integration (S201), an output voltage from the battery is detected and an average of the output voltages detected for a predetermined time period is calculated (S202), an average of the residual battery capacities obtained by the operation for a predetermined time period is calculated (S203), a reference voltage corresponding to the calculated average of residual battery capacities is referred to (S204), the reference voltage and the average voltage is compared (S205), and the predetermined charge efficiency is set variably based on a result of the comparison (S206).

Abstract: Providing a reference voltage to a cross point memory array. The invention is a cross point memory array and some peripheral circuitry that, when activated, provides a reference voltage to a cross point array. The peripheral circuitry can be activated before, after or during selection of a specific memory plug. If the peripheral circuitry is activated during selection, only the unselected conductive array lines should be brought to the reference voltage. Otherwise, all the conductive array lines can be brought to the reference voltage.

Abstract: A nonvolatile semiconductor memory device of the present invention includes: a first booster circuit for generating a first voltage higher than a voltage supplied by an external power source, the first booster circuit being used for writing or deleting of data; a second booster circuit for generating a second voltage higher than the voltage supplied by the external power source, the second booster being used for reading of data; a regulator for controlling the first voltage, the regulator being connected to an output terminal of the first booster circuit; and a reference voltage generator circuit for generating a reference voltage input to the regulator. The nonvolatile semiconductor memory device is characterized in that: a power source of the reference voltage generator circuit is connected via a transistor to an output terminal of the second booster circuit; and the nonvolatile semiconductor memory device includes a section for allowing the transistor to be electrically conductive immediately after a start of an operation for writing or deleting of data.

Abstract: A voltage generating circuit includes a plurality of field effect transistors at least partially having gates same in conductivity type but different in impurity concentration. The gates are different in impurity concentration by not less than one digit.

Abstract: In order to stably generate a high voltage of a prescribed level, a Vpp detection circuit which is activated in response to an activation signal for comparing the high voltage with a reference voltage is forcibly brought into an active state for a prescribed period under control of an initial control circuit.

Abstract: PROBLEM TO BE SOLVED: To reduce a standby current. SOLUTION: Internal reference voltage is generated by inputting a desired voltage obtained by resistively dividing a power supply voltage with a 1st resistor divider part 2 to a 2nd resistor divider 11 via a 1st current mirror circuit 3, inputting a desired voltage resistively divided by this resistor divider part 11 to a 3rd resistor divider part 26 via a 2nd current mirror circuit 12, and dividing the desired voltage by this resistor divider part 26. The 2nd resistor divider part 12 is composed of a plurality of P-channel MOS transistors 14A, 14B of different sizes connected in series, and is adjusted so as to generate a voltage Va at the time of a normal operation by selecting a desired MOS transistor out of the MOS transistors 14A, 14B, and to generate a voltage Vb lower than the voltage Va at the time of standby.

Abstract: An integrated current-to-voltage conversion circuit converts a first current to an output voltage representative of the first current. The circuit includes a first contact pad and second and third contact pads capable of being coupled across a first resistor. A first operational amplifier has a first input coupled to the first contact pad for producing a first voltage thereat, a second input for receiving a reference voltage, and a first output coupled to the third contact pad. A second voltage appears at the third contact pad. A second operational amplifier has a second output at which a third voltage appears, a first input coupled to the second output, and a second input coupled to the second contact pad. The output voltage is substantially equal to the difference between the second and third voltages.

Abstract: A method for cancelling load regulation, based on level shifting the reference, is proposed. In this architecture, the load current is monitored, sensed, and used to dynamically adapt the effective value of the reference voltage. The proposed architecture reduced a 2.5% load regulation droop to a mere 0.2%, without compromising system stability.

Abstract: A test on a desired internal voltage is easily and accurately conducted without increasing current dissipation or the number of pads. A driving circuit receiving a reference voltage from a reference voltage generating circuit has a high input impedance and low output impedance, and generates a voltage substantially at the same voltage level as the reference voltage received, and transmits the generated voltage to a pad with a current driving capability larger than the driving current capability of the reference voltage generating circuit.