Abstract: The introduction of new high power devices like integrated gate commutated thyristors (IGCTs) and high voltage insulated gate bipolar transistors (IGBTs) accelerates the broad use of pulse width modulation (PWM) voltage source converters in industrial and traction applications. This paper summarizes the state-of-the-art of power semiconductors. The characteristics of IGCTs and high voltage IGBTs are described in detail. Both the design and loss simulations of a two level 1.14 MVA voltage source inverter and a 6 MVA three-level neutral point clamped voltage source converter with active front end enable a detailed comparison of both power semiconductors for high power PWM converters. The design and the characteristics of a commercially available IGCT neutral point clamped PWM voltage source converter for medium voltage drives are discussed. Recent developments and trends of traction converters at DC mains and AC mains are summarized.

Abstract: This paper surveys circuit innovations in ferroelectric memories at three circuit levels: memory cell, sensing and architecture. A ferroelectric memory cell consists of at least one ferroelectric capacitor, where binary data are stored, and one or two transistors that either allow access to the capacitor or amplify its contents for a read operation. Once a cell is accessed for a read operation, its data are presented in the form of an analog signal to a sense amplifier, where it is compared against a reference voltage to determine its logic level. The circuit techniques used to generate the reference voltage must be robust to semiconductor processing variations across the chip and the device imperfections of ferroelectric capacitors. We review six methods of generating a reference voltage, two being presented for the first time in this paper. These methods are discussed and evaluated in terms of their accuracy, area overhead and sensing complexity. Ferroelectric memories share architectural features such as addressing schemes and input/output circuitry with other types of random-access memories such as dynamic random-access memories. However, they have distinct features with respect to accessing the stored data, sensing, and overall circuit topology. We review nine different architectures for ferroelectric memories and discuss them in terms of speed, density and power consumption.

Abstract: In this paper we present a bandgap circuit capable of generating a reference voltage of 0.54 V. The circuit, implemented in a submicron BiCMOS technology, operates with a supply voltage of 1 V. In the bandgap circuit proposed we use a non-conventional operational amplifier which achieves virtually zero systematic offset, operating directly from the 1 V power supply. The bandgap architecture used allows a straightforward implementation of the curvature compensation method. The proposed circuit achieves 5 ppm / K of accuracy without requiring additional operational amplifiers or complex circuits.

Abstract: PROBLEM TO BE SOLVED: To allow a circuit for lighting a fluorescent lamp to inhibit source voltage fluctuation and fluctuation of light rays caused by fluctuation of ambient temperature. SOLUTION: A power detecting part 5 detects via a resistance R1 a voltage signal proportional to a current in a fluorescent lamp and detects via voltage dividing resistances R3, R4 a voltage signal proportional to the voltage of the fluorescent lamp, and the instantaneous values of the two voltage signals at every moment are multiplied via a multiplying circuit U41, with this multiplication output smoothed via a low-pass filter U42 to detect the average power value S5 of the fluorescent lamp. Next, a control circuit 4 compares the average power value S5 with a reference voltage value Vref via an error amplifier U2, and controls the drive circuit U3 of an inverter circuit 3 via a voltage controlled oscillator U1 so that the difference therebetween becomes zero, thereby varying the switching frequencies of switching elements T1, T2.

Abstract: A 8 b-wide single-ended simultaneous bidirectional transceiver test chip in a 0.4 /spl mu/m CMOS process allows study of the major challenges in high-performance, low-cost parallel-link design. This paper shows the I/O cell and placement of I/O pads in each chip. Data pins are laid out with different signal return configurations to study cross-talk in parallel links. In the I/O cell, the open-drain output driver is broken down into 4 legs ratioed 1:2:4:4 for swing control. The line is terminated on each side with a pMOS resistor, whose gate voltage is adjusted externally for impedance control. Two externally-adjustable reference voltages (VrefH and VrefL) are multiplexed to generate the local reference voltage (Vref) to decode incoming data. The I/O design operates at a bit time equal to 4 fanout-of-4 delays (FO4=delay of an inverter driving a load of 4 identical inverters and is 193 ps at a 3.3 V supply in this run). The bidirectional links operate at 2.4 Gb/s/pin (1.2 Gb/s in each direction), with 200 mV minimum signal swing on each side for the pins with worst-ease cross-talk.

Abstract: A power factor control circuit for an AC to DC power converter includes an inductor receiving AC rectified power. The charging time of the inductor is controlled by a switching circuit based on a comparison between a DC bus voltage and a fixed reference voltage. The circuit operates without an AC rectified line sensing network, and without a current-sensing resistor connected to the source of the MOSFET switch.

Abstract: In this article, the current-sampling error has been investigated in the field-oriented control of an AC machine by a PWM inverter. The expression of the harmonic current due to a low-pass filter has been studied analytically from the reference voltage vector in the SVPWM strategy. The fundamental components of the current-sampling error causes improper torque regulation while the high-frequency ripple of the error introduces permissible gain of the current regulators with a resultant impairment in dynamic behavior and limited stability range of the control systems. It has been proposed that the magnitude and phase error from the filter can be avoided with delayed sampling. The effectiveness of the delayed sampling was verified through simulations and experimental results including steady state and dynamic responses.

Abstract: A method and apparatus to dynamically modify the internal compensation of a low drop out linear voltage regulator is presented. The process involves using zero mobile compensation; when the output pole of the voltage regulator moves, a compensating zero is moved toward higher frequencies. This compensation zero is used to compensate the effect of a second pole in the loop gain. The circuit includes an input stage having an error amplifier. The error amplifier includes a differential stage output coupled to an output terminal of the buffer stage. An output stage of the circuit includes an output transistor having a conduction terminal connected to an output terminal of the voltage regulator, and having a control terminal coupled to the output terminal of the buffer stage. Additionally, a variable compensation network is connected between the differential stage output and a voltage reference. This variable compensation network can include an RC circuit having a resistive transistor. The resistance value of the resistive transistor is modulated according to the output load current of the voltage regulator, thereby changing the location of the compensating zero.

Abstract: A method for detecting the content of a selected memory cell (106) in a memory cell array (100) includes the steps of charging a drain of the selected memory cell to a ground potential, charging a source of the selected memory cell to a predetermined voltage potential (V1), detecting the voltage level on the drain and comparing the detected voltage level with a reference voltage level (Vreference), thereby producing a comparison result.

Abstract: A semiconductor memory device has a memory cell array that outputs cell current to data sensing amplifiers and reference current to reference amplifiers. The reference amplifiers convert the reference current to a reference voltage. The data sensing amplifiers use the reference voltage to convert the cell current to a data voltage signal. According to a first aspect of the invention, reference current is supplied to a reference amplifier from two parallel data paths, each having approximately equal numbers of transistors of two types, one type of which is always switched on, the other type switching on and off. According to a second aspect of the invention, each data sensing amplifier, and the reference amplifier to which it is connected, receive currents from parts of the memory cell array having identical layouts.

Abstract: An internal power supply voltage generation circuit includes a main amplifier that supplies a current from an external power supply node to an internal power supply line in accordance with the difference between a reference voltage from a reference voltage generation circuit and an internal power supply voltage on the internal power supply line. The current supply amount by the main amplifier is adjusted by a level adjust circuit, according to the difference between the external power supply voltage and the reference voltage. The internal power supply voltage generation circuit can suppress reduction in the internal power supply voltage in the vicinity of the lower limit area of the differential power supply voltage.

Abstract: A buck switching DC-to-DC regulator having a resistor and capacitor in combination across the storage inductor to measure output current and voltage. The resistor connects to the input of the inductor and the capacitor to the output of the inductor. The junction of the resistor and capacitor connects to an error amplifier for controlling the switching regulator. The regulator may be paralleled for more output current by connecting the outputs together and providing a common reference voltage to all the regulators.

Abstract: An apparatus for determining the state of a multistate memory cell. The apparatus includes three sense amplifiers, each with an associated reference cell which produces a reference voltage for input to each of the sense amplifiers. The apparatus includes circuitry which allows the reference cell currents to be varied to produce the reference voltages or pairs of reference voltages needed to accurately determine the threshold voltage and hence state of a programmed or erased memory cell.

Abstract: A connectionless paralleling and load sharing system and method for power sources are presented. The invention provides a dynamic feedback adaptive control system that enables proper load sharing among paralleled power sources without the need for interconnection therebetween. Only the individual source's voltage and current are sensed by its controller. These output parameters are then used to modify a reference voltage used by the controller to control the source's output waveform. This reference voltage compensation is accomplished through two feedback control loops, an outer loop for the voltage compensation and an inner loop for the current compensation. The outer loop includes an integration of the voltage error between the desired voltage and the actual voltage sensed at the source's output. The inner loop is filtered and operates in a proportional fashion to rapidly adjust the output. Through proper constant selection the control system and method of the invention provides load sharing control proportional to an individual source's power supplying capacity, i.e. on a per unit basis. This allows the use of supplies of different rating in a single paralleled environment. This system and method are particularly well suited for systems requiring uninterruptible power supplies.

Abstract: A method for voltage detection and lockout. The method of one embodiment first compares a reference voltage to a supply voltage to determine whether the voltage supply voltage is greater than the reference voltage. The reference voltage is validated by determining whether the reference voltage is at least a valid voltage potential. An unlock signal is generated if the supply voltage is greater than the reference voltage and if the reference voltage is valid.

Abstract: A bias circuit suitable for use with a radio frequency linear power amplifier compensates for amplifier gain compression by providing bias current responsive to an amplitude of an RF signal to be amplified at a bias current gain greater than unity. The bias circuit comprises a minimal number of active and passive components and is suitable for implementation in a range of process technologies. Bias current gain may be configured over a range of less than to greater than unity gain by adjusting a reference voltage supplied to the bias circuit and by adjusting a resistor value included within the bias circuit. In implementation, the bias circuit is configured to have a bias current gain that complements a characteristic gain compression associated with a particular radio frequency power amplifier.

Abstract: A monitor device for monitoring the activity of an individual to provide an alarm for anomalous by the individual. The device includes a triaxial accelerometer adapted to measure simultaneously measure acceleration in three orthogonal, linear axes and generate a voltage output identifying the amplitude and frequency of detected motion by the individual in each axis. Also included is interface electronics for receiving the voltage outputs and buffering the voltage outputs to generate a first reference voltage for each axis of the accelerometer. Amplifier electronics amplifies each voltage output and compares each voltage output to the first reference voltage to produce a digital signal. A microcontroller receives the digital signal to compare it to an adjustable second reference voltage. The microcontroller is programmed to discriminate between normal activity and anomalous activity by identifying sensor activity within sequences of preselected time intervals and sending an alarm signal upon detection of the anomalous activity. An alarm for receiving the alarm signal and signaling an alarm completes the device.

Abstract: A control circuit for a piezo transformer based power supply for a fluorescent lamp includes driver circuitry generating pulse waveforms for providing excitation to primary inputs of the piezo transformer, and circuitry for regulating lamp current and the voltage across the piezo transformer primary inputs. The frequency of the pulse waveforms is varied in response to the magnitude of lamp current to maintain a predetermined desired lamp current as represented by a current reference signal. The duty cycle of the driver circuitry is varied in response to the magnitude of the voltage across the piezo transformer primary inputs to maintain a predetermined desired piezo primary voltage as represented by a voltage reference signal. The piezo transformer is operated as close to resonance as possible, contributing to greater circuit efficiency. The driver circuitry in the control circuit employs four transistors arranged as a full bridge with respect to the piezo transformer primary inputs. The phase of drive signals supplied to one pair of the transistors is varied with respect to the phase of drive signals supplied to the other pair, thereby varying duty cycle and average voltage of the piezo transformer primary inputs. A controller integrated circuit contains a number of components of the control circuit, enabling its use in a variety of piezo-based power supply applications.

Abstract: A clock generator has a duty cycle correction circuit that adjusts the duty cycle to 50%. A modulator is an inverter with extra source-limiting transistors in series to the power and ground supplies. A control voltage of about Vcc/2 is applied to the source-limiting transistors, causing them to operate in the linear region with limited current. A slow-slew output from the modulator is buffered by a driver. The driver output is filtered by a linear detector with a series resistor and input capacitor. The detector output is compared to a reference voltage of Vcc/2 by an error amp. The error amp generates the control voltage fed back to the modulator. An output capacitor creates a dominant pole with the error amp to ensure stability. A variable-threshold gate can be added between the driver output and the detector to separately adjust the measurement threshold voltage from the reference voltage to the error amp.

Abstract: Apparatus and methods are described for the voltage control of power converters in which the input and output voltages of the converter are not sensed directly but are derived from an inductor voltage which in turn is derived by sensing an instantaneous inductor current.

Abstract: Presented is a low supply voltage oscillator circuit having at least one capacitor to be controlled, connected between first and second voltage references, and a circuit for charging and discharging the capacitor to be controlled. The oscillator circuit also includes at least first and second stages having symmetrical structures in a mirror-image configuration and being connected between the first voltage reference and the second voltage reference and connected together through a memory element. The oscillator circuit also includes respective primary switches for alternately charging the capacitors in a controlled fashion.

Abstract: A pipeline ADC includes an input stage and a first group of subsequent stages, wherein the input stage includes a unity gain amplifier having an input for receiving an analog input signal, an output, and first and second comparators each having a first input coupled to the output of the unity gain amplifier. The first comparator has a second input for receiving a first reference voltage an first output, and the second comparator has a second input for receiving a second reference voltage and an output. The input stage includes a full adder coupled to the output of the first comparator, a second input coupled to the output of the second comparator, and an output producing MSB bit information. Each subsequent stage includes an amplifier of gain greater than 2 having an input and an output, a summer having a first input coupled to the output of the amplifier of gain greater than 2, a second input, and an output, a switching circuit operating in response to the outputs of the first and second comparators of a previous stage to selectively couple one of a third reference voltage, a fourth reference voltage, and fifth reference voltage to a second input of the summer. Each subsequent stage also includes a full adder having a first input coupled to the first output, a second input coupled to the second output, the full adder producing bit information less significant than the MSB bit information. In the described embodiment, the third reference voltage is a negative reference voltage, the fourth reference voltage is a ground reference voltage, the fifth reference voltage is a positive reference voltage. The first reference voltage is midway between the third reference voltage and the ground reference voltage, and the second reference voltage is midway between the ground reference voltage and the fifth reference voltage. Each switching circuit operates to decode with three states represented by the first and second comparators of the previous stage. The plurality of stages include a second group of subsequent stages of lower binary bit significance than the first group of subsequent stages, the first group of subsequent stages being recursively self-calibrated, the second group of subsequent stages being not self-calibrated. The pipeline ADC is included in a self-calibrating pipeline ADC including a plurality of analog-to-digital conversion units and a recursive calibrating section operable for calibrating errors associated with an immediately preceding first conversion unit.

Abstract: An active termination circuit for clamping a signal on a transmission line in an electronic device in a tri-state mode is described. The active circuit includes a tri-state output buffer and a bottom clamping transistor coupled to GND and the tri-state output buffer having a bottom clamping transistor control node arranged for clamping the signal at about GND. A bottom threshold reference transistor coupled to a first reference voltage supply configured to supply a first reference voltage. The bottom threshold reference transistor provides a first bias voltage to the bottom clamping transistor control node that biases the bottom clamping transistor control node at about a first threshold voltage above GND where the first threshold voltage represents a threshold voltage of the bottom clamping transistor. A top clamping transistor coupled to VDD and the tri-state output buffer having a top clamping transistor control node arranged for clamping said signal at about VDD and a top threshold reference transistor coupled to a second reference voltage supply configured to supply a second reference voltage. The top threshold reference transistor provides a second bias voltage to the top clamping transistor control node that biases the top clamping transistor control node at about a second threshold voltage from VDD where the second threshold voltage represents a top clamping transistor threshold voltage.

Abstract: A surface-mounted permanent magnet synchronous machine drive and a method of controlling the machine drive. Flux weakening and current regulating loops cooperate to provide automatic transition to the flux weakening mode (operation above base speed), regardless of DC bus voltage, load or other operating conditions. The modulation index (d) is used as a condition for automatic start of flux weakening operation is very useful because this point can be easily changed by software when necessary, regardless of the value of DC bus voltage. This feature provides significant performance improvement. No look-up tables are used in the flux weakening loop. The on-set point for flux weakening is automatically adjusted, and may be changed through software. An appropriate d-axis current component is injected over the entire speed range, providing the maximum available torque (which corresponds to the q-axis current component).

Abstract: A voltage control system and methodology for maintaining internally generated voltage levels in a semiconductor chip. The method comprises the steps of intermittently sampling an internal voltage supply level during a low power or “sleep” mode of operation; comparing the internal voltage supply level against a predetermined voltage reference level; and, activating a voltage supply generator for increasing the internal voltage supply level when the internal voltage supply level falls below the predetermined voltage reference level. The voltage supply generator is subsequently deactivated when the voltage supply level is restored to the predetermined voltage reference level. The sampling cycle may be appropriately tailored according to chip condition, chip temperature, and chip size. In one embodiment, the voltage control system and methodology is implemented in DRAM circuits during a refresh operation. The voltage levels that are suitable for sampling including DRAM band-gap reference voltage, boost wordline line voltage, wordline low voltage, bitline high voltage and bitline equalization voltages.

Abstract: The present invention relates a flyback circuit for zero voltage switching {ZVS} in continuous mode {CCM} and discontinuous mode {DCM}, which circuit minimized loss generated when electrifying parasitic diode of MOS transistor {MOSFET} that is secondary side switch of synchronous rectifier and which also enabled ZVS in whole range of discontinuous mode {DCM}. Particularly it contains a synchronous rectifier driver that delays the gate drive signal that is outputted from pulse width modulation part after which the driver compares it with reference voltage that is outputted from pulse width modulation part and then the driver amplifies result value so as to supply it as the drive signal for synchronous rectifier part, a level change device that drives the synchronous rectifier gate, changing the level of gate drive signal that is outputted from gate drive device, and an insulating transformer that transmits the drive signal that is outputted from synchronous rectifier driver, to the level change device side. Wherewith it inverts the output signal of the pulse width modulation part in driving the synchronous rectifier gate, resulting in minimization of loss occurred at time of electrification of parasitic diode of MOS transistor {MOSFET} that is secondary side switch so that it makes effect to enhance efficiency letting it perform zero voltage switching {ZVS} under fixed frequency condition in discontinuous mode {DCM}.

Abstract: A bandgap reference circuit capable of operating at low voltage provides an adjustable bandgap reference voltage. The bandgap reference circuit includes a proportional to absolute temperature (PTAT) current source, a bias current source, two resistors and a transistor. The base of the transistor couples to the IPTAT current source and the emitter of the transistor couples to the bias current source. The bandgap reference circuit also includes two resistors. The first resistor couples between the emitter and the base of the transistor, and the second resistor couples to the base of the transistor. The first resistor receives a portion of the bias current and provides a current proportional to a base-emitter voltage of the transistor. The second resistor receives the PTAT current and the current proportional to the base-emitter voltage of the transistor and provides a reference voltage which remains substantially constant over temperature and which is proportional to a silicon bandgap voltage. The ratio of the first and second resistors determines the proportionality of the reference voltage to the silicon bandgap voltage. Thus, by adjusting the ratio of the two resistors a reference voltage less than the silicon bandgap voltage can be obtained.

Abstract: A system and a method for handling power ramping and AM in wireless transmissions using NCE modulation schemes. A closed loop power control loop (304) with two modes is used for the power ramping and AM burst portions of a wireless transmission. During key-up (ramping) no AM transmission takes place. The power control loop (304) is in a conventional normal mode of operation during key-up, that is, it acts as a conventional power loop. Normal operation mode for the power control loop (304) is in a fast (high speed) closed loop. During ramping, the variable gain amplifier (or VGA) (336) of the AM Control Loop (306) is adjusted such that the baseband signal level matches the reference voltage used for ramping. Thus, prior to an AM burst transmission, the sampled IF voltage, xV, is made equal to the sampled output voltage of the power amplifier (302). When ramping up is complete and AM begins, the control voltage to the VGA (336) of the AM Control Loop (306) is held constant for the duration of the AM burst. During AM, the power control loop (304) is set to a slow control loop mode. Control of the power control loop (304) is achieved by comparing the power amplifier detector output with the calibrated baseband signal converted from IF.

Abstract: The invention is a circuit and method of limiting the charging current voltage from a power supply net work applied to an individual cell of a plurality of cells making up a battery being charged in series. It is particularly designed for use with batteries that can be damaged by overcharging, such as Lithium-ion type batteries. In detail, the method includes the following steps: 1) sensing the actual voltage level of the individual cell; 2) comparing the actual voltage level of the individual cell with a reference value and providing an error signal representative thereof; and 3) by-passing the charging current around individual cell necessary to keep the individual cell voltage level generally equal to a specific voltage level while continuing to charge the remaining cells. Preferably this is accomplished by by-passing the charging current around the individual cell if said actual voltage level is above the specific voltage level and allowing the charging current to the individual cell if the actual voltage level is equal or less than the specific voltage level. In the step of bypassing the charging current, the by-passed current is transferred at a proper voltage level to the power supply. The by-pass circuit a voltage comparison circuit is used to compare the actual voltage level of the individual cell with a reference value and to provide an error signal representative thereof. A third circuit, designed to be responsive to the error signal, is provided for maintaining the individual cell voltage level generally equal to the specific voltage level. Circuitry is provided in the third circuit for bypassing charging current around the individual cell if the actual voltage level is above the specific voltage level and transfers the excess charging current to the power supply net work. The circuitry also allows charging of the individual cell if the actual voltage level is equal or less than the specific voltage level.