Abstract: In a voltage-fed PWM inverter, the relation between the reference voltage and the output voltage is nonlinear due to the dead time effect and the voltage drop of the switching devices. The nonlinear voltage distortion invokes serious problems such as current waveform distortion and deterioration of the performance. Especially, the clamping of current around the zero crossing point is the most serious problem in the low-frequency region. In this paper, the analysis of the zero current clamping phenomenon is discussed. From this analysis, a novel distorted voltage compensation method which eliminates zero current clamping is presented. Experimental results are also presented to demonstrate the validity of the proposed method. >

Abstract: This paper describes a bandgap voltage reference circuit that operates with a 3 V power supply and is compatible with a digital CMOS process. The use of a simple circuit topology results in a small silicon area of 0.07 mm/sup 2/, a power consumption of 1 mW and a high power supply rejection over a wide frequency band. The circuit realizes a temperature coefficient of 85 ppm//spl deg/C and a standard deviation of 20 mV without trimming. >

Abstract: A single-ended input but internally differential 10 b, 20 Msample/s pipelined analog-to-digital converter (ADC) is demonstrated with 4 mW per stage using a single 5 V supply. The prototype ADC made of an input sample and hold (S/H) plus 8 identical unscaled pipelined stages consumes 50 mW including power consumed by a bias generator and two internal buffer amplifiers driving common-mode bias lines. Key circuits developed for this low-power ADC are a dynamic comparator with a capacitive reference voltage divider that consumes no static power, a source-follower buffered op amp that achieves wide bandwidth using large input devices, and a self-biased cascode biasing circuit that tracks power supply variation. The ADC implemented using a double-poly 1.2 /spl mu/m CMOS technology exhibits a DNL of /spl plusmn/0.65 LSB and a SNDR of 54 dB while sampling at 20 MHz. The chip die area is 13 mm/sup 2/. >

Abstract: A variable slew control for output circuits is disclosed. The slew control circuit automatically adjusts the rate in which voltage on a slew node is driven to a reference voltage, minimizing noise at the output device driver. The variable slew control decreases the slew rate of the slew node during periods when di/dt is at a high level, but allows the voltage on the slew node to drop at faster rates during times when di/dt at the output driver is low.

Abstract: A scanning circuit for an array of pressure responsive sensor points which permits the sensitivity of the circuit to be controlled. In particular, the sensitivity of the circuit may be controlled by controlling a test and/or reference voltage used with the circuit and different sensitivity or resolutions may be provided for different areas of the array. The circuit also provides enhanced interelectrode isolation, permitting a single test voltage to be utilized to scan all sensor points on a given input electrode and further reduces the time required to scan the array by reducing trace capacitance discharge time and by inhibiting processing for sensor points which are not of interest. The accuracy of pressures being sensed is also enhanced by adjusting the test voltage to compensate for load variations.

Abstract: A power supply comprising a coil a switching transistor for establishing a conduction path between the input terminal and the coil during an on-time and for interrupting the conduction path between the input terminal and the coil during an off-time. A diode is provided for sustaining a conduction path for the current through the coil (20) upon interruption of the conduction path between the input terminal (20) and the coil and an apparatus is provided for varying the ratio between the on-time and the off-time of the switching transistor in response to a difference between an output voltage across the load and a first reference voltage (VI). The power supply exhibits an improved efficiency by maintaining the ratio constant if the output voltage lies between two reference values. Within this voltage window defined by the two reference values the power supply is self-regulating, as a result of which the control may be disabled so that the efficiency is improved.

Abstract: We propose an on-chip high-voltage generator circuit for low-voltage EEPROMs composed of a pMOSFET-based charge pump circuit driven by bootstrapped clock generators. The voltage gain per unit stage does not suffer from the threshold voltage drop. The device implemented in a 1.2 /spl mu/m CMOS technology operates as low as 1 V.

Abstract: There is provided an improved method for bulk (or byte) programming an array of flash EEPROM memory cells. A negative voltage is applied to the substrate of the array. A reference voltage of zero volts is applied simultaneously to the drain regions of selected memory cells that are to be programmed. There is also applied simultaneously the same reference voltage of zero volts to the control gates of the selected memory cells. The present invention provides for low current consumption and fast programming of the memory cell, which require only a single, low voltage power supply. The endurance reliability is greater than 100,000 cycles.

Abstract: A voltage regulator for electrically programmable non-volatile memory cells includes a gain stage which is supplied a voltage from a voltage booster connected to a supply voltage reference, having an input terminal connected to an output of a voltage divider and an output terminal connected to a pull-up transistor of a pull-up and pull-down differential pair to output the regulated voltage for programming at least one column or bit line of the memory cells. The voltage regulator also includes a second gain stage having an input terminal connected to a second output of the voltage divider. The second stage has an output connected to turn on the pull-down transistor in the complementary pair upon the regulated voltage exceeding a predetermined value.

Abstract: PURPOSE:To restrain variations in the discharge amount by controlling the value of a current fed to a discharge heater. CONSTITUTION:In a constitution where 8 groups of discharge heaters h1 to h64 are driven separately, using common signals COM 1 to COM 8 and segment signals SEG1 to SEG8, a reference voltage value of a constant current circuit 1404 corresponding to each of the common signals is preset, and a applicable reference voltage value is supplied through a D-A converter 1402 when each of the common signals is on. Thus optimal current values can be set for each of the heaters h1 to h64.

Abstract: An analog-to-digital converter (ADC) circuit is proposed that utilizes the linearity of the single-bit first-order sigma-delta in a first mode technique. In a second mode, successive approximation is used to convert the remaining voltage from the first conversion to increase the resolution without significantly increasing the conversion time. Both operations can be made in the same hardware, and only a counter is needed as decimation filter so that the converter becomes both area and power efficient. A channel of the ADC implemented in standard CMOS occupies an area of 40/spl times/1640 /spl mu/m/sup 2/. The control logic and reference voltage generation circuits, common for the ADC array, occupy a similar area. Estimated power consumption per ADC channel is about 0.5 mW including reference voltage generation. The conversion speed per ADC channel is 12.8 ksamples/s at a clock rate of 3.4 MHz. The ADC concept is suitable whenever a high resolution at a moderate speed is needed.

Abstract: The output impedance in a CMOS output driver stage is programmed and compensated by complementary current mirrors that are MOS devices in series with each of the conventional pull-up and pull-down devices. The conduction of these additional complementary devices is controlled according to complementary programming signals that are compensated for variations in manufacturing process parameters as well as for changes in temperature. A P-type programming signal may be referenced to +VDD and be produced from an N-type programming signal referenced to GND by the action of a gate voltage mirror that includes symmetrical N-type and P-type FET's in series. The N-type programming signal may be produced in the first instance from the gate voltage of an N-type FET used in a feedback loop that servos an external programming voltage to track an internally generated reference voltage. That gate voltage exhibits variations that reflect differences attributable to both process variations and to temperature. Those exhibited variations are communicated by a current mirror to a gate voltage mirror that produces the complementary programming signals, and which themselves constitute negative feedback. The complementary current mirrors are of known of gain, which in conjunction with knowing the value of VDD, allows the determination in advance of a definite table of programming resistance values versus output impedances.

Abstract: A transmission power control circuit comprises a control data table in which digital data of a monitor voltage depending on a transmission power level for a plurality of values of transmission frequency and a plurality of values of transmission power are stored. A D/A converter converts selected values of the digital data to an analog signal as a reference voltage. The transmission power is controlled so that the monitor voltage becomes equal to the reference voltage.

Abstract: A level detection circuit for monitoring the level of a power supply voltage and producing an output signal at power on for resetting various system elements powered by the supply voltage when the supply voltage reaches a predetermined level. The detection circuit, which is powered by the supply voltage includes a voltage reference circuit which produces a reference voltage having a magnitude which is relatively independent of the power supply voltage. A translator circuit functions to produce a translated voltage indicative of the supply voltage magnitude and which is comparable in magnitude to the reference voltage when the supply voltage is at a suitable level such that the system will accept a power on reset pulse. A comparator circuit functions to compare the reference voltage with the translated voltage and cause an associated output circuit to issue the reset pulse. The reset circuit typically includes a one shot circuit, the output of which is logically ORed with the amplified comparator output. The amplified comparator output functions to hold the system elements in a reset state at very low supply voltages and the one shot output functions to reset the system elements once the supply voltage is at a sufficiently high level.

Abstract: A determinate power source control for an integrated circuit (10) includes a variable voltage regulator (16), which is operable to receive a supply voltage on the input thereof and output a regulated voltage for input to the integrated circuit (10). A voltage adjustment circuit (22) is operable to generate a voltage adjustment value V ADJ for input to the voltage regulator (16) to determine the voltage output thereby. In a determinate operating mode, the voltage adjustment circuit (22) varies the V ADJ value to cause the regulator (16) to vary the regulated output voltage to the integrated circuit (10). For each value, the operating speed of the integrated circuit (10) is determined and this information stored in a table (24). Thereafter, the voltage adjustment circuit (22) is placed in an operating mode wherein the voltage adjustment value associated with the optimum operating speeds of the integrated circuit (10) is selected and input to the voltage regulator (16). The voltage adjustment circuit (22) utilizes an on-chip ring oscillator (38) to generate a series of pulses which are input to a counter (48). The counter (48) and ring oscillator (38) are operated for a predetermined amount of time with reference to crystal oscillator (30), and then this value latched into latch (52).

Abstract: Generation of an output voltage (28) greater than that of a reference voltage (20) is accomplished using a self starting low voltage charge pump (10). A start-up clock circuit (12) comprising a ring oscillator (40) is used to generate a ting oscillator clock signal (63) which can be used allow the charge pump (10) to begin operation before an external clock signal (44) is available.

Abstract: A method for generating a programmable bandgap output reference voltage (V REF31 ) and a voltage reference circuit (31) have been provided. The voltage reference circuit (31) includes a pair of bipolar transistors (33, 34), a resistor (36), an operational amplifier (32) and a plurality of field effect transistors (38, 39, 41) configured to generate a current (I 1 ') having a positive temperature coefficient. In addition, the voltage reference circuit (31) includes a resistor (46), an operational amplifier (44), another plurality of field effect transistors (47, 48) which, in conjunction with one (34) of the pair of bipolar transistors, generates a current (I 2 ') having a negative temperature coefficient. The current (I 1 ') having the positive temperature coefficient is summed with the current (I 2 ') having the negative temperature coefficient to form a current having a zero temperature coefficient, which is used to develop a voltage having a zero temperature coefficient.

Abstract: The present invention relates to an improvement in an EL driver including a second power supply voltage producer for producing second supply voltage for use in driving an EL lamp using a battery serving as a first power source, a third supply voltage producer for producing third supply voltage that is higher than the first supply voltage and lower than the second supply voltage, and a driving signal supplier for supplying an AC driving signal to an EL driving means when driven by the third supply voltage. The level of the AC driving signal is increased in two steps. The EL driver semiconductor device characteristic of the high-voltage efficiency and high threshold voltage can therefore be driven by low voltage.

Abstract: Apparatus is provided for detecting faults in a sensor providing an output voltage representative of aeration of a combustible mixture. The apparatus comprises a control box which checks whether the value of a reference voltage with which the output voltage is compared to control the aeration is suitable for causing an intended value of the aeration to be maintained.

Abstract: An algorithmic converter system includes an algorithmic converter having a loop gain substantially less than two for converting an analog input signal to a redundant digital code; and a digital computation unit for converting the redundant digital code to a digital output signal by computing a polynomial of a radix, said radix being substantially equal to the loop gain, wherein the redundant digital code specifies coefficients of the polynomial. The redundancy extends the analog input conversion range with respect to the voltage reference of the algorithmic converter. Moreover, if the algorithmic converter has a maximum offset of Voffmax, a reference voltage of Vref, and a loop gain less than 2/(1+Voffmax /Vref), then loop offset will not cause differential nonlinearities. Nonlinearity is further reduced by digitally compensating for variations in the loop gain. The method includes measuring the loop gain of said algorithmic converter, and setting the radix of the computation unit equal to the measured value of the loop gain. Preferably the loop gain is measured by converting two reference voltages to obtain two sets of digits from the algorithmic converter, and employing a successive approximation technique that alternately computes an offset value and adjusts the radix. For the redundant signed digit (RSD) algorithmic converter, rapid convergence is obtained using a zero reference voltage and a non-zero reference voltage. For a conventional restoring (CR) algorithmic converter, however, positive and negative reference voltages are used.

Abstract: A substrate bias generator for an integrated circuit has a charge pump driven by an oscillator. The oscillator is enabled and disabled to save power and control the voltage-level itself for the substrate bias. An enabling circuit senses the substrate voltage and enables the oscillator when the substrate voltage rises above a bias set by a programmable reference voltage. The enabling circuit which senses the voltage on the substrate draws no active current from the substrate. The sensing circuit includes a transistor with only its bulk terminal connected to the substrate; the source, gate, and drain of this sensing transistor are not connected to the substrate. A differential comparator compares the output of the sensing transistor to the programmable reference voltage and enables the oscillator when the sensing transistor output is lower than the reference voltage. The sensing transistor attenuates large swings in the substrate voltage to provide the differential comparator with a small voltage swing which keeps the differential comparator operating near its optimum design point. Since no active current is drawn from the substrate when sensing the substrate voltage, no IR voltage drops can develop from the enabling and sensing circuit. Thus latch-up immunity is improved and substrate noise is reduced.

Abstract: In a disk drive, the read-write heads of the disk drive should be parked during a power failure. The kinetic energy of the spinning rotor is used to move the head away from the disk's surface. A high voltage is produce from the low voltage spindle motor by using a BEMF voltage to step up the voltage in a voltage supply capacitor to a higher voltage by enabling or disabling a switch connected to a comparator. When the switch is turned on, it shorts the rectified voltage in the stator windings to ground in order provide a current path for a current formed in the coils by the BEMF. When the current reaches a predetermined level, the switch is turned off. The current flows through the voltage supply capacitor so that its voltage is "kicked-up" by the inductance of the windings and by the BEMF still present in the stator windings. This increased voltage is used to park the heads and to brake the motion of the spindle. Two control feedback loops are used to more efficiently enable the voltage conversion. A current comparator compares the current in coils to a reference current and turns the switch off when the current is at a predetermined level. A voltage comparator compares the voltage across the load with a reference voltage and turns the switch off when the voltage is above a predetermined value.

Abstract: A brushless dc motor unit has 3-phase armature windings, a permanent-magnet rotor, a dc power supply having a motor drive voltage and a midpoint voltage that is one half of the motor drive voltage, and an electronic commutation circuit. Back emf voltages at armature winding terminals are individually delayed by less than 90° and the delayed voltages are individually provided to the positive input terminals of voltage comparators. To the negative input terminals of the comparators is commonly provided a sawtooth-wave comparator reference voltage having a frequency proportional to a current rotor speed and an amplitude whose center voltage is the midpoint voltage. Outputs of the comparators cause a control circuit to transmit signals to control the electronic commutation circuit so as to provide 3-phase dc power to the armature windings. A basic reference voltage regulates the amplitude of the comparator reference voltage, and the value of the basic reference voltage can be changed according to a rotor speed or motor current so as to adjust the delay angle of the comparator outputs. The time constant of the phase delay circuits may be increased when the rotor speed is below a predetermined speed.

Abstract: A supply voltage detect circuit is described which generates a control signal indicating the status of VCC to be at 5.0 or 3.3 volts. This control signal is used to generate analog reference signals used by A/D and/or D/A circuitry in an audio processing integrated circuit and by other circuitry to control clock frequencies or current drive.

Abstract: Described herein is a reference voltage circuit which includes, in combination, a bit line and first and second word line reference transistors connected to the bit line and operative to be turned on with a reference pulse simultaneously with the turning on of the word lines in the main memory circuit. First and second ferroelectric capacitors are connected to each of the first and second word line reference transistors, respectively, and to a source of plate line switching voltage, and a first precharging transistor is connected between the first ferroelectric capacitor and ground potential. A second precharging transistor is connected between the second ferroelectric capacitor and a further source of switching voltage, so that the first and second ferroelectric capacitors are polarized in a ONE and ZERO state in the manner identical to the logic states of the ferroelectric capacitors in the main ferroelectric memory circuit. Thus, when the first and second word line reference transistors turn on, the bit line reference voltage is raised above ground potential by the sum of the voltages of the first and second ferroelectric capacitors. This in turn causes the bit line reference voltage, BL, to track the voltage variations of the ferroelectric capacitors in the main memory circuit, thus providing improved margins for the BL and BL complementary signals which are sensed by a plurality of sense amplifiers for the main memory circuit.

Abstract: A detection and alarm circuit for protection of electronic components includes a fan motor current sensing resistor for producing a pulse that is amplified and introduced to a frequency-to-voltage converter for generating a filtered and processed voltage level for application to a voltage comparator. A reference voltage circuit supplies a voltage level to the comparator for matching with the filtered and processed voltage level and depending on the mismatch, an output signal is introduced to a transistor switch for operating an alert alarm device.

Abstract: PROBLEM TO BE SOLVED: To prevent the over-strokes of a piston from being generated and restrict efficiency from being lowered by providing an inverter control means for increasing the output voltage of an inverter circuit by each reference voltage value if the reference value of the top dead center is greater than the calculated top dead center position of the piston. SOLUTION: In a vibration type compressor, the AC power converted from DC power is supplied from an inverter circuit 25 to an annular coil of a compressor, thereby a piston communicating with the coil vibrates in the cylinder axial direction, and refrigerant compression is performed. At this time, the analog position signal of the piston from a displacement detector 21 is input to a top dead center position calculation means 28, and the top dead center being the maximum value at the upper end position of the piston is calculated here. The top dead center position from the top dead center position comparison means 29 and the top dead center reference value are compared, if the reference value is greater than the top dead center position, a waveform generation means 31 outputs the waveform signal to a base drive circuit 26 so that the inverter output voltage is made greater by the reference voltage. COPYRIGHT: (C)1997,JPO

Abstract: A protective circuit intended to protect a load against excessive input voltage includes a depletion mode MOSFET, i.e., a MOSFET which is conductive when its Vgs = 0. Various alternative embodiments are described including those where the gate of the depletion mode MOSFET is tied to its source or to ground or some other reference voltage, where the gate of the MOSFET is switched at the onset of an excessive voltage condition, and where the gate of the MOSFET is controlled by negative feedback. The protective protecting IC loads in automobile form a condition known as load dump.

Abstract: A protection device for a micro-controller chip comprising a heat sink, a cooling fan, and an overheat alarm The heat sink is adapted to be mounted on a micro-controller chip and is capable of dissipating heat generated by the micro-controller chip The cooling fan disperses the heat dissipated by the heat sink into the surrounding atmosphere The overheat alarm includes a temperature sensor, a voltage comparator, an oscillator, and alarm sound generator The temperature sensor converts a temperature of the heat sink into electrical signals and outputs a voltage proportional to the temperature of the heat sink A voltage comparator compares the voltage output from the temperature sensor with a reference voltage signal and outputs a comparator output voltage The oscillator generates and outputs an oscillating voltage signal The alarm sound generator is enabled by the comparator output voltage from the voltage comparator for generating an alarm sound by operating a speaker in accordance with the input oscillating voltage signal from the oscillator