Abstract: A method and a system in a virtual machine system controlling a simultaneous run of one or more operating systems (OS's) by use of a virtual machine control program on a real machine including a storage area for each virtual processor constituting the virtual machine for saving a status of each virtual processor, for storing an active flag indicating whether or not the virtual processor is in the active state, and for storing a running priority specified for each virtual processor by the control program wherein when an OS being running issues an instruction to set the processor to the wait state, the instruction is directly executed, a state of the virtual processor being running is stored in the status save area, a processor is selected from processors for which the nonactive state is set, a virtual processor is selected according to the running priority from a group of virtual processors not in the wait state nor in the active state, and a content of the status save area of the virtual processor is set to the processor.

Abstract: The functions of two virtual operating systems (e.g., S/370 VM, VSE or IX370 and S/88 OS) are merged into one physical system. Partner pairs of S/88 processors run the S/88 OS and handle the fault tolerant and single system image aspects of the system. One or more partner pairs of S/370 processors are coupled to corresponding S/88 processors directly and through the S/88 bus. Each S/370 processor is allocated from 1 to 16 megabytes of contiguous storage from the S/88 main storage. Each S/370 virtual operating system thinks its memory allocation starts at address 0, and it manages its memory through normal S/370 dynamic memory allocation and paging techniques. The S/370 is limit checked to prevent the S/370 from accessing S/88 memory space. The S/88 Operating System is the master over all system hardware and I/O devices. The S/88 processors access the S/370 address space in direct response to a S/88 application program so that the S/88 may move I/O data into the S/370 I/O buffers and process the S/370 I/O operations. The S/88 and S/370 peer processor pairs execute their respective Operating Systems in a single system environment without significant rewriting of either operating system. Neither operating system is aware of the other operating system nor the other processor pairs.

Abstract: A method is described which permits a user of an Intelligent Work Station (IWS) in an SNA type network in which communication with the host processor employs LU 6.2 advanced program to program protocols and in which the host processor does not assign a dedicated virtual machine to the user during the period the user is active on the system, to notify the system of the user's current terminal address so that distributed applications programs having component parts distributed at the host and the IWS may be executed. When resident counterpart programs of distributed applications are executed by assigning each LU 6.2 conversation to an idle virtual machines from a preestablished pool of virtual machines created by the host processor, rather than to a dedicated virtual machine, the prior art methods that are based on associating the current address of the user with the address of the dedicated virtual are no longer operable. The new method does not require the user to notify the system that the user's IWS is active, since the user may want to run programs that do nor involve the host processor and may not want to be distracted with communications from the host and other users. In accordance with the new method a distributed application is provided at the terminal which is invoked by the user when a decision is made to provide the current terminal address to the host. The distributed application issues an LU 6.2 ALLOCATE verb requesting a conversation with the counterpart program resident at the host. The counterpart program is executed at the host by a virtual machine from the pool and establishes a data structure where the USERID of the user and the terminal address of the IWS are associated. The data structure is stored at a location which is scanned by all subsequent LU 6.2 conversation requests from the host and other users for a match of USERIDs. When a match occurs the associated current terminal address of the USERID is inserted into the request and sent to the IWS by the system.

Abstract: A virtual machine system which includes a plurality of virtual machines by using a computer system of a multi-processor configuration having a plurality of real instruction processors and a real main storage which is divided into a plurality of storage regions to be allocated to the virtual machines, respectively. Each of the virtual machines is so organized as not to make access to the regions allocated to the other virtual machines. When one and the same virtual machine includes a plurality of real instruction processors, invalidation of entry of a buffer storage of another real instruction processor as conditioned by execution of a predetermined instruction by a real instruction processor is performed only for the other real instruction processor assigned to the same virtual machine as the real instruction processor and is inhibited from affecting the real instruction processors assigned to the other virtual machines.

Abstract: A description is given of the microprocessor configurer system, or Micon, which was designed to provide support for computer hardware designers. The objective of Micon is to reduce the time required to construct a hardware system. The approach to achieving this objective rests on two points: capturing and disseminating design expertise in a format that actively assists designers, and providing a tool environment that supports all aspects of computer design. Artificial intelligence provides design synthesis and the acquisition of design expertise. Databases provide consistent views of data to all tools. Networking allows the system to efficiently share common resources, such as the database, across many users of the system. Micon is compared to related design systems, its architecture is described, examples of its use are given, and a set of experiments to test its viability is described. >

Abstract: A quantitative performance study of two-phase locking in a parallel database machine using a simulation-based methodology is presented. The DBSIM simulation methodology uses a Petri-net model at the higher level and a queuing network model at the lower level. The Petri net model captures the characteristics of parallelism and synchronization at the workload level, while the queuing network model captures queuing aspects of the system at the physical resource level. Transactions in a workload are specified using a performance-oriented specification language based on the transaction component graph: a data-flow graph with database operators. The transaction specifications are translated into Petri-net representations to drive the simulation experiments. Results of an analysis of a two-phase locking strategy with machine sizes ranging from 4 to 256 processors are presented. >

Abstract: This paper presents an overview of the software and hardware architecture of Britton-Lee Corporation’s Intelligent Database Machine (the IDM). The IDM was designed to provide quality database performance at a moderate cost. Communication between the host computer and the IDM is discussed, as are the issues involved in dividing the total work load between the host computer and the IDM backend machine. In addition, certain performance characteristics of the IDM are presented.

Abstract: An address translation apparatus is provided which has an address translation look-aside buffer with an entry composed of a real address field, virtual machine identifier field and space identifier field. For the translation look-aside buffer entry to be used by a general virtual machine which uses a plurality of address spaces, a virtual machine identifier for discrimination of a general virtual machine is stored in the virtual machine identifier field, and information used in discriminating an address space is stored in the space identifier field. For the translation look-aside buffer entry to be used by a dynamic address translation off (DATOFF virtual) machine which uses a single address space, an identifier commonly assigned to a group of DATOFF virtual machines is stored in the virtual machine identifier field, and a control block address used in discriminating a DATOFF virtual machine is stored in the space identifier field.

Abstract: A virtual machine system in which a plurality of operating systems (OS's) can run on one computer including a physical main storage (physical MS), and at least one physical extended storage (physical ES), each operating system (OS) of the OS's having a virtual MS on the physical MS and at least one virtual ES on the at least one physical ES. The system includes a first address translator for translating a virtual ES address designated by an instruction issued by one OS of the OS's on a virtual space generated by the one OS on one virtual ES of the at least one virtual ES of the one OS to a virtual physical ES address on the one virtual ES based on the virtual ES address and an address of an ES relocation table on the virtual MS of the one OS or an ES relocation register in the computer, the one virtual ES being on one physical ES of the at least one physical ES of the computer, and a second address translator for translating the virtual physical ES address to a physical ES address on the one physical ES based on the virtual physical ES address and a start address of the one virtual ES in the one physical ES.

Abstract: Scalable shared-memory multiprocessors (those with non-uniform memory access times) are among the most flexible architectures for high-performance parallel computing, admitting efficient implementations of a wide range of process models, communication mechanisms, and granularities of parallelism. Such machines present opportunities for general-purpose parallel computing that cannot be exploited by existing operating systems, because the traditional approach to operating system design presents a virtual machine in which the definition of process, communication, and grain size are outside the control of the user. Psyche is an operating system designed to enable the most effective use possible of large-scale shared-memory multiprocessors. The Psyche project is characterized by (1) a design that permits the implementation of multiple models of parallelism, both within and among applications, (2) the ability to trade protection for performance, with information sharing as the default, rather than the exception, (3) explicit, user-level control of process structure and scheduling, and (4) a kernel implementation that uses shared memory itself, and that provides users with the illusion of uniform memory access times.

Abstract: PURPOSE:To enable resource allocation quantity to be dynamically made proper by allowing a resource allocation control part to collect data on a resource using quantity in a virtual computer and to decide the sufficiency and insufficiency of the resource allocation quantity for each virtual machine. CONSTITUTION:The respective virtual computers 11-13 have the resource having quantity measuring parts 15-17 which examines the using quantity of allocated resource when the computers are operated. The resource allocation control part 14 collects the data on the resource using quantity in the respective virtual computers 11-13, decides the sufficiency and the insufficiency of the resource allocation quantity for the respective virtual computers 11-13 and dynamically makes it proper. Thus even when load is fluctuated in the optional virtual computer, as the reallocation of the resource dynamically balanced can be executed, the resource can be effectively utilized. Besides, the throughput and the processing ability of the whole system can be improved.

Abstract: It is demonstrated how commercially available hardware description languages, which are normally used for hardware design verification at low to medium levels of modeling abstraction, can be used to optimize the design of complex real-time systems exhibiting concurrency. A high-performance, loosely coupled multiprocessor FASTBUS master intended for real-time event-processing applications is modeled. The performance of such a system depends on a large number of parameters that interact in a complex way, so that it becomes very difficult to make reliable tradeoffs in the design of the system architecture using an analytical approach. Given a high-level behavioral hardware description language and its simulator, it is shown that it is relatively easy to develop an executable model that provides a test bench for optimization of the architecture. >

Abstract: PURPOSE:To heighten the flexibility of a virtual compute system by constituting a system so that device allocation information to a guest operating system can be changed freely. CONSTITUTION:A device managing means (I/O driver) 2 controls an I/O instruction from the guest operating system based on the device allocation information 1 representing the allocation of each device on the guest operating system. A constitution change means (constitution change utility) 4 can change the device allocation information 1 by a console 5 consisting of a CRT, a keyboard, and a mouse, etc. A constitution change informing means 3 informs the change of the device allocation information by the constitution change means 4 to a device managing means 2. A system loader (VMM loader that is a part of a monitor in the virtual computer system) 6 develops the device allocation information on a memory at the time of starting up the system.

Abstract: PURPOSE:To simultaneously operate the quest OSs (operating system) different plural architecture by executing the different type OSs, which have different architecture, on the same VM monitor (execution control program) in a virtual computer system. CONSTITUTION:This computer system is constituted to include a real computer system and the VM monitor in order to present virtual computer environment to the quest OS. The real computer system is composed of real device controllers 1a, 1b,...,1m, a real interruption controller 2, an unfair instruction trap mechanism 3 and a central processing unit 4. When a quest OS11 tries to execute an instruction, which has possibility to confuse the virtual computer environment, the unfair instruction trap mechanism 3 informs the VM monitor of the operation. When the real interruption controller 2 informs the VM monitor of the interruption, the central processing unit 4 refers a real interruption writing table and control is delivered to an interrupting handler.

Abstract: A method to preserve system resources during the execution of distributed application programs in an SNA type data processing network that supports program to program communication between an Intelligent Work Station (IWS) and a host processor in accordance with SNA Logical Unit 62 protocols when a Virtual Machine Pool Manager exists at the host processor and functions to, (1) create a pool of virtual machines at the host processor that are brought to a run ready state prior to any program to program communication, (2) dynamically assign an idle run ready virtual machine to process each request from the IWS involving one application program so that sequential requests from the one program are assigned to different ones of the idle virtual machines and run concurrently, and 3) provide a Pool Manager Data Structure for use by the Pool Manager during the step of dynamically assigning the idle run ready virtual machines in the pool The method comprises the steps of providing an Operating System for the IWS which attaches an identifier (ID) to predefined segments of the resident application program that include LU 6 2 type conversation requests The ID are transmitted to the host at the time a request is transmitted to permit the Virtual Machine Pool Manager to decide, based on the transmitted ID and previously received IDs whether to assign the request to an active or idle virtual machine in the pool If The ID is the same as a segment being run on an active machine, the request is assigned to the same machine If the transmitted ID is different, the request is assigned to an idle machine in the pool Therefore, predefined segments can be executed concurrently on different assigned virtual machines at the host only when the application program segments have been assigned different IDs by the terminal operating system

Abstract: This paper is concerned with the design of intelligent subsystems that interface actuators and sensors to intelligent supervisors for robot work-cells. Benefits of our approach include removal of low level computation and stringent real-time constraints from the superviser, potential for combining and interpreting information from sensor combinations, and provision of a uniform information interface for disparate devices. Our approach to the design and organisation of these subsystems is based on the concept of virtual devices . We demonstrate the applicability of the concept by describing the design and implementation of an intelligent controller for a sensory gripper.

Abstract: The process involves creating and running a special program in the virtual machine which is to be accorded suspend and resume control functions. The suspend/resume control function program is run first before a user's task is run. The special suspend/resume program seizes control over the virtual machine's external interrupt controls and modifies them to direct all incoming interrupts to the program itself rather than allowing CMS of the virtual machine to handle interrupts as is normally done. With incoming interrupts being sent to the suspend/resume program for analysis and response, incoming commands that generate such interrupts may be responded to and sub-routines contained within the suspend/resume task program may be employed to save all of these addressing registers and general register contents. This effectively takes a snapshot of the present status and intermediate result conditions existing in the user's task program operation at the time the interrupt occurred, thus enabling the restoration at a later time from the point at which suspension of the task occurred. The suspend/resume task program operates to modify the interrupt controls of the virtual machine to create a suspension of operation of the user's task program by enabling the virtual machine only for external interrupts.

Abstract: PURPOSE: To carry out the host and guest processes independently of each other in order to eliminate the overhead and to attain the flexible control by providing a means which applies an interruption to a host mechanism from a virtual (guest) computer when the communication is required to the host mechanism. CONSTITUTION: A means 11 which dynamically assigns a host mechanism 1 which instructs the start of execution of a virtual computer 2 to a specific CPU 10 in each cluster 1, a means 11 applies an interruption to the host mechanism 1 from the computer 2 when the mechanism 1 assigns selectively the execution of the computer 2 to its own CPU 10 or another CPU 10 and the working computer 2 needs the communication to the mechanism 1 are provided. Then the host and guest processes are carried out independently of each other via plural CPUs 10. In such a constitution, the host overhead caused by the inter- host interference is reduced in a virtual computer system. Then the more flexible control of resources is attained and the load can be decentralized. COPYRIGHT: (C)1990,JPO&Japio

Abstract: A novel approach to both automatic data path synthesis and architecture optimization of existing machines is reported. This approach features innovations in the concept of automatic synthesis as well as in the method used in the system implementation. This work exhibits two new features: (1) at the level of the automatic architecture synthesis process, the automatic design of specific image processing automata is done from emulation results of a more general-purpose machine for image processing applications; and (2) at the level of system implementation, taking into account the constraints of design (speed, area, etc.), the method used to search the design space is a stimulated-annealing-based algorithm. Therefore, systematic optimization of the architecture is performed, leading to the design of a 'child automaton' at the architectural level from two files: the hardware description of the emulator machine; and the control data-flow graph. >

Abstract: It is noted that users of the future will require access to objects and services that are scattered across large networks and that the workstation can mold these objects and services into complete systems. The author suggests that in order to talk about the role of the workstation in such systems, one must have an idea of how they will be organized. He describes one model for organizing such systems and shows how the workstation might fit in. >

Abstract: An overview is given of the Comandos project of the European Strategic Programme for Research on Information Technology (ESPRIT). The initial phase of the project was devoted to the definition of the Comandos virtual machine and resulted from contributions of the different partners in the project. Then several testbed implementations were started to validate the basic ideas of the architecture. The virtual machine and its supporting architecture are described. Some design issues faced in the development of the prototype are presented, with particular reference to the object memory. The current status of the project and future plans are briefly discussed. >

Abstract: PURPOSE: To simplify the emulation of a VM (virtual machine) monitor by emulating I/O in an an OS (operating system) as a usual console. CONSTITUTION: When an I/O instruction is issued from a transmission origin program 2 to a transmission destination program 3 in order to transmit a message, the VM monitor 6 refers to the definition body of a first virtual I/O device establishing means 1. The designated I/O device executes I/O-interruption to the OS 8 in which the transmission destination program 3 exists, when this I/O device is decided to be the I/O device defined as for inter-VM communication use. Then, when the I/O instruction for reading in the message is issued from the transmission destination program 3, it controls so as to copy the contents of the designated message copied before in the VM monitor 6 through the first and a second virtual I/O device establishing means 1,5 to a memory in the OS 8 designated by the transmission destination program 3 through the first and a third virtual I/O device establishing means 1,7. Thus, the emulation processing of the VM monitor is executed simply. COPYRIGHT: (C)1991,JPO&Japio

Abstract: PURPOSE:To automatically executing a performance measurement by the benchmark job of a virtual machine to a full virtual machine and an object without worrying about measuring environment and to reduce man hour by using a communicating function between the virtual machine. CONSTITUTION:By a performance measurement starting command from a console device 6, a communication processing part 5 of a virtual machine 4 opens a message log file 7 and indicates the starting of a processing to a virtual machine 15 of a user. The machine 15 outputs a text 18 to indicate the name of an operating system 17. A processing part 5 obtains an applicable benchmark job 14 from a corresponding table 11, and convert-inputs it through a spool file 12 to a benchmark job 14 of the machine 15. The machine 15 executes the job 14, outputs the data to the text 18, send them to a machine 4, stores them in the file 7 and outputs them as editing data 10 when the processing of the system 17 is completed, and the data are analyzed and evaluated.

Abstract: PURPOSE:To realize a mechanism to execute plural resident virtual computers operated at high speed equivalently with each other and its control method and to suppress the increase of a quantity of hardware at a minimum level by providing an adding means and a holding means for an address constant. CONSTITUTION:The virtual address 1 of a virtual computer VM is converted to the absolute address 5 of the VM via an address conversion part 2, etc. And in a resident VM, conversion from the address of a memory device in the VM to the absolute address 15 of a real CPU is performed by adding a leading address in an area in a real memory device in a host to which the VM is allocated. Therefore, on an address constant holding part 8, the leading address of the area on the real memory device in the real CPU to which the VM is allocated is set. And the output itself of an address constant addition part 7 is designated as the address 15 via the holding part 8, the addition part 7, a VM classification indicating bit 13, and a selector 14. In such a way, the acceleration in the resident VM can be realized, and the mechanism to execute the plural resident VMs operated at high speed equivalently with each other and its control method can be realized.

Abstract: PURPOSE:To know the number of instruction steps by providing a counter means which adds or subtracts the software instructions one by one for each execution of the soft instructions to realize plural virtual machines which execute the independent operating systems via a single real computer. CONSTITUTION:When the number of closed execution instruction steps are measured in a real computer, the contents of a step register 1 are reset to 0 with a software instruction when a step counting operation is started. Then the contents of the register 1 are read out with a software instruction when the step counting operation is through. In other words, the contents of a saving area of the register 1 included in a virtual computer control block of the virtual machine counting the steps are previously rewritten into 0 before start of the step counting operation. Then a subject virtual machine is started. Then the saved value of the register 1 contained in the control block is read out after the step counting operation. Thus the number of executed steps can be known.

Abstract: PURPOSE: To easily interrupt and restart the processing of a task by correcting the program interruption control of a task virtual computer in response to the detection of an interruption command and enabling only the response to an external interruption, if the command is detected in a task program. CONSTITUTION: In a virtual computer in which a given task or job is executed just before a job itself is executed, a special small-sized task program is executed. This special small-sized program is the one in which the technique facilitating the interruption restarting of an actual task to be executed in the virtual computer is made implemental. When the special program for interruption restarting operation is loaded, the program first moves the program itself to a storage area or a reservation area when it is normally empty so that the operation may not be overwritten or interfered when the task program is executed. This interruption restarting program controls the external interruption of the virtual computer. Thus, the interruption of the task in process in the virtual computer and the subsequent restarting become safe and easy.

Abstract: PURPOSE:To attain the execution of an I/O instruction and I/O end processing in one stage and to improve the performance of line control in a virtual computer system by allowing plural operating systems to use a line control part in common. CONSTITUTION:The line control part constituted of an I/O instruction execution means 50, an I/O end information means 51 and a line control table 52 is arranged on a system common address space 7. The control part 5 is constituted so as to be used in common by virtual computers alpha, beta by means of a virtual storage control function common use means 4 and the control part 5 can be used in common by the operating systems 2, 3. Consequently, the execution of an I/O instruction and I/O end processing can be attained in one stage and the performance of line control can be improved.

Abstract: Proposes a number of assignment and scheduling policies, ranging from asymmetric handling of operating system (OS) processing on designated OS processors, to the symmetric scheduling of OS processing on any available processor. These policies are evaluated under a variety of load conditions. Small systems, with up to three processors, are studied experimentally using the Mach operating system on a VAX-11/784. A discrete event simulator is used to study larger and more varied system configurations. For asymmetric systems, the results show that the OS preempt policy, which gives OS processing preemptive priority over application processing, provides the best performance in almost all situations. >

Abstract: A general technique for creating realistic synthetic images on massively parallel machines is presented. The methodology attempts to fully exploit the completely distributed structure of these novel computers by assigning individual processors to regions of space. Unfortunately, most examples of massively parallel computers in use today consist of only two-dimensional processor grids rather than true three-dimensional ones. Anticipating future developments, a three-dimensional virtual machine model is first defined which directly "interprets" a newly devised programming language called MCM. Graphics algorithms are developed for this virtual machine and then implemented in this new language. To actually create synthetic images, MCM programs are translated into the native language of some appropriate physical device, usually a Connection Machine, where they are eventually executed. The overall procedure for generating synthetic images on a massively parallel machine consists of two major components. The first is a modeling activity which serves to initialize processor memories with specified optical parameters. The vast number of such memories coupled with slow data rates between the processor grid and the external world suggest that the processors themselves should help distribute lighting information from a relatively small amount of input. Once processor memories have been initialized after modeling, images are created using a two-phase rendering method. The first step in this procedure simulates light propagation and its interaction with matter by using principles of wave mechanics. After intensity data has been distributed throughout a processor grid by the lighting simulation, the second rendering phase collects this information into a screen image via a massively parallel ray-tracing procedure.