Abstract: METHOD OF INTER-PROCESS COMMUNICATION IN A DISTRIBUTED DATA PROCESSING SYSTEM ABSTRACT A multi-processor, multi-tasking virtual machine comprises processes, messages, and contexts. Processes communicate only through messages. Contexts are groups of related processes. The virtual machine is implemented in a distributed data processing system comprising a plurality of individual cells coupled by a local area network (LAN). Each cell may comprise one or more processes and/or contexts, A network interface module (NTM) provides the interface between any individual cell and the LAN. To facilitate message transmission between processes resident on different cells, each NIM provides addressing modes allowing messages to be sent to processes according to the processes names. Cells may be added to or deleted from the LAN, and processes may be created or deleted, without disrupting the LAN operations.

Abstract: VIRTUAL SINGLE MACHINE WITH MESSAGE-LIKE HARDWARE INTERRUPTS AND PROCESSOR EXCEPTIONS ABSTRACT A multi-processor, multi-tasking virtual machine comprises processes, messages, and contexts. Processes communicate only through messages. Contexts are groups of related processes. The virtual machine makes all hardware devices appear to be processes, in that the occurrence of an event on a device causes a message to be generated and sent to another process for handling. The receiving process performs all operations required to handle the event. Thus a variety of hardware devices can be connected and disconnected from the system without interrupting its operation and without necessitating extensive software revisions.

Abstract: A file control system for virtual machines capable of executing simultaneously a plurality of operating systems in a single computer system under control of a virtual machine monitor for controlling the operating systems, wherein interface means for file input/output operation are provided between the virtual machine monitor and the operating systems for allowing the virtual machine monitor to manage a plurality of files owned by the virtual machines.

Abstract: A computer system for controlling virtual machines each given a different identification number. The system comprises mask registers and I/O interruption queues, each provided with the same numbers as the virtual machines, and corresponding to any one of the identification numbers. An interrupt handling in any one of the virtual machines can be carried out directly by using a pair of corresponding mask registers and I/O interruption queues without an interposition of the VM monitor.

Abstract: A method to manage the operation of a coprocessor in a virtual memory type data processing system in which an Input/Output channel and an Input/output channel controller interconnect the coprocessor to the main processor and system memory. A Virtual Resource Manager (VRM) comprising a group of interrelated software programs function in the system to establish virtual machines that execute application programs concurrently. A Coprocessor Manager component of the VRM establishes a Virtual Machine in which the compressor executes application programs that cannot be executed on the main processor. The coprocessor is mounted on an integrated circuit card which is inserted into a `mother board` socket which contains the main processor and related components.

Abstract: The software virtual machine (SVM) concept is described as a methodology to reduce the manpower required to implement and maintain finite element software. A SVM provides the engineering programmer with high‐level languages to facilitate the structuring and management of data, to define and interface process modules, and to manage computer resources. A prototype finite element system has been successfully implemented using the SVM approach. Development effort is significantly reduced compared to a conventional all‐FORTRAN approach. The impact on execution efficiency of the SVM is described along with special procedures developed to minimize overhead in compute‐bound modules. Planned extensions of capabilities in the SVM used by the authors are outlined.

Abstract: We have implemented Smalltalk-80 on an instruction-level simulator for a RISC microcomputer called SOAR. Measurements suggest that even a conventional computer can provide high performance for Smalltalk-80 by abandoning the 'Smalltalk Virtual Machine' in favor of compiling Smalltalk directly to SOAR machine code, linearizing the activation records on the machine stack, eliminating the object table, and replacing reference counting with a new technique called Generation Scavenging. In order to implement these techniques, we had to find new ways of hashing objects, accessing often-used objects, invoking blocks, referencing activation records, managing activation record stacks, and converting the virtual machine images.

Abstract: Operating systems of virtual machines periodically issue diagnostic instructions during the normal operation. A virtual machine control monitor selects the earliest one of monitoring times for virtual machines and sets it in the clock facility in a bare machine. If the monitor receives the diagnostic command from a virtual machine before expiration of the monitoring time, it re-sets the clock facility. Otherwise, the monitor issues a machine check interrupt command to the virtual machine in which the monitoring time has expired.

Abstract: Virtual Instruments1 is an experimental programming environment for developing electronic test and measurement (T&M) applications. Intended users are test engineers, who are not programmers, but computer literate domain specialists. Unlike traditional programming environments, that provide weak support for a broad range of applications, virtual instruments provides strong support for a specific application. The programming paradigm is bottom-up synthesis of layers of virtual machines — called virtual instruments — using human interface models from the application domain, so that software development occurs without writing code. The object-oriented view of the world has proven a natural fit. Implementation was in Berkeley Smalltalk on a SUN workstation.

Abstract: A processor for the Smalltalk-80↑ programming language is described. This machine is implemented using a standard bit slice ALU and sequencer, TTL MSI, and NMOS LSI RAMS. It executes an instruction set similar to the Smalltalk-80 virtual machine instruction set. The data paths of the machine are optimized for rapid Smalltalk-80 execution by the inclusion of a context cache, tag checking, and a hardware method cache. Each context is only partly initialized when created, and has no memory allocated for it until a possibly non-LIFO reference to it is created. The machine is microprogrammed, and uses a simple next micro-address prediction strategy to obtain most of the performance of pipelining without the attendant complexity. The machine can execute simple instructions at over 7M bytecodes per second and has a predicted average throughput of 1.9M bytecodes per second.A processor for the Smalltalk-80↑ programming language is described. This machine is implemented using a standard bit slice ALU and sequencer, TTL MSI, and NMOS LSI RAMS. It executes an instruction set similar to the Smalltalk-80 virtual machine instruction set. The data paths of the machine are optimized for rapid Smalltalk-80 execution by the inclusion of a context cache, tag checking, and a hardware method cache. Each context is only partly initialized when created, and has no memory allocated for it until a possibly non-LIFO reference to it is created. The machine is microprogrammed, and uses a simple next micro-address prediction strategy to obtain most of the performance of pipelining without the attendant complexity. The machine can execute simple instructions at over 7M bytecodes per second and has a predicted average throughput of 1.9M bytecodes per second.

Abstract: A multi-processor, multi-tasking virtual machine (Fig. 2) comprises processes, messages, and contexts. Processes communicate only through messages. Processes may be grouped into contexts of related processes. Contexts may also be nested (Fig. 8). Communication may be made between processes in different or related contexts, or at the same context level, or between nested contexts. According to one message transmission mode (Fig. 7), a message may be sent to each process with a given name within one context, thus ensuring that all processes with the same name at the same context level can be communicated with individually without knowing how many there are or where they are located. The virtual machine makes all hardware devices appear to be processes, in that the occurrence of an event on a device causes a message to be generated and sent to another process for handling (Fig. 5). The receiving process performs all operations required to handle the event. Thus a variety of hardware devices can be connected and disconnected from the system without interrupting its operation and without necessitating extensive software revisions.

Abstract: PURPOSE: To gather monitor information of each virtual computer by providing two or more of, at least, either of addresses of a measured area on a main storage designated with a monitor information gathering counter register or an OS and identifiers of virtual computers. CONSTITUTION: Hardware counter groups 9-1 and 9-2 are provided in a hardware monitor mechanism 8 of a CPU 2, and monitor information for running of a control program (VMCP) are gathered by counter groups 9-2 and 9-1 when a virtual computer (VM) runs, and '1' is set to a running mode display register 14 in case of running of the VMCP and '0' is set there in case of running of the VM. When an instruction is issued, its extended instruction is processed if the register 14 is '1', that is, the VMCP issues the instruction, and the instruction of a conventional hardware monitor is processed if the register 14 is '0', that is, the VM issues the instruction. COPYRIGHT: (C)1987,JPO&Japio

Abstract: The CAOS system is a framework designed to facilitate the development of highly concurrent real-time signal interpretation applications. It explores the potential of multiprocessor architectures to improve the performance of expert systems in the domain of signal interpretation. CAOS is implemented in Lisp on a (simulated) collection of processor-memory sites, linked by a high-speed communiications subsystem. The "virtual machine" on which it depends provides remote evaluation and packet-based message exchange between processes, using virtual circuits known as streams. To this presentation layer, CAOS adds (1) a flexible process scheduler, and (2) an object-centered notion of agents, dynamically-instantiable entities which model interpreted signal features. This report documents the principal ideas, programming model, and implementation of CAOS. A model of real-time signal interpretation, based on replicated "abstraction" pipelines, is presented. For some applications, this model offers a means by which large numbers of processors may be utilized without introducing synchronization-necessitated software bottlenecks. The report concludes with a description of the performance of a large CAOS application over various sizes of multiprocessor configurations. Lessons about problem decomposition grain size, global problem solving control strategy, and appropriate service provided to CAOS by the underlying architecture are discussed.

Abstract: In a virtual machine system comprising real processing units, a mode-changing arrangement comprises a mode memory 18 for storing mode data indicating a mode in a non-virtual machine, for execution of real operating systems on one of the real central units, a mode with virtual machine monitoring for the control of units selected from among the real central units by way of virtual central units, and a virtual machine operating system for using virtual machine operating systems on the virtual central units. Loaded into a program 17 instruction register 6, a program instruction accesses the mode memory in order to select one of the mode data by way of selected data item. The selected data item is loaded into the mode register in such a way as to cause the virtual machine system to operate in the mode indicated by this data item stored in the register.

Abstract: PURPOSE:To execute the input/output processing of a virtual computer at a high speed by preserving the contents of the magnetic disk device of the virtual computer on a virtual memory space and replacing the input/output processing for the magnetic disk device to the data transfer between virtual memories. CONSTITUTION:A virtual computer is composed of virtual hardware resources, a memory is composed of a virtual memory 32, a CPU is composed of a virtual CPU 41 and an input output device is respectively composed of a virtual device of peripheral equipment such as a console, a line printer and a card reader, and a magnetic tape MT and a magnetic disk 42. When the virtual disk space system is applied, a virtual disk device 42 owned by the virtual computer exists at the exclusive-use virtual memory space, that is to say, a virtual disk space 31. An input/output instruction to the virtual disk 42 is all simulated by a virtual computer monitor VMM, and the data transfer is executed between the virtual disk space 31 and the virtual memory 32 of the virtual computer.

Abstract: A screen-oriented process is used for configuring devices in an open computer system. The computer system includes an operating system having device drivers, and the operating system can be run as a virtual machine on a virtual resource manager wherein a procedure is used to bind the device drivers of the operating system and the virtual resource manager and an attached device on a particular port of an adapter using device dependent information. The configuring process initially requires the creation of device dependent information files for a plurality of devices and device types, and these files are installed in the computer system. Each file includes adapter specific information and device specific information consolidated in a single file. The user may invoke a configuration command, and the system responds by displaying a plurality of commands such as add, change, delete and show and prompts the user to choose a command. If the add command is chosen, the system displays a list of predefined devices and adapters of the device type specified by the user and prompts the user to choose from among the predefined devices and adapters in the list When the user makes a choice, the system then asks the user whether the device dependent information for the chosen device and adapter should be displayed so that the user has the option of changing either or both the adapter specific information and the device specific information in one step.

Abstract: This chapter contains sections titled: A Babel of Tools, Reinventing the Wheel, Engineers' Natural Language, Inventing the Wheel Once, Working Hand in Hand, Virtual Probes into Virtual Machines, Solutions and Dreams, For More Information

Abstract: One class of reconfigurable parallel processing systems is based on the use of a large number of processing elements which can be partitioned into multiple virtual machines. Each virtual machine is controlled by one or more control units. The multiple control units in such a system share a common secondary storage for programs. The control units use paging to transfer programs to their primary memories. One design problem is determining the optimal service rate for the secondary storage of the control units, where the "optimal" is characterized by maximum processor utilization. The PASM parallel processing system is used as a example system to study this problem. The implementation of virtual memory on the PASM control system memory hierarchy is discussed and a queueing network model for the memory hierarchy is developed. Based on assumed values for parameters that characterize the expected task environment, an optimal service rate is derived from the model. The values of the parameters in the model can be varied to determine the impact these changes would have on system performance. Simulation results verifying various aspects of the model are presented and the results are generalized.

Abstract: PURPOSE:To attain the application of a virtual computer system from a remote terminal or an optional terminal by connecting a virtual computer and the terminal with a communication circuit CONSTITUTION:Each terminal can utilize the function of an RAVM which converts local data stream into a remote data stream using a communication control program VTAMG by means of this VTAMG At the same time, functions other than the RAVM can also be applicable If the OS of a VM 12 to be tested produces an input/output instruction, for example, an SIO instruction produced from the OS is calculated by an AVM (synonym) for a virtual calculation monitor 10) with a privileged instruction exception Then the conversion of real addresses is carried out in terms of channels and the branching is given to the RAVM in a processing mode equal to the SIO An RAVM EXIT transfers the contents of the input/output buffer of the VM to the buffer of the RAVM within a range that can be processed by the RAVM Then an interruption is reflected to the program situation word PSW, etc of a server VM and reset to the AVM

Abstract: The paper presents the low-level languages implemented up to date to program the PAPIA machine.

Abstract: This paper describes the more novel features of a virtual machine designed to support a nest-free, highlevel programming language. The machine is a stack based machine using tagged words and polymorphic operators. The design reflects the project's major goal of very high level support for the language allowing for straightforward compilation and direct support of a high-level debugging facility. The language for which the machine was designed is modular and does not allow the nesting of procedures or modules. It is strongly typed and provides for parametric (generic) type modules. Exceptions and exception handling are provided, but as yet only sequential processing is supported, although parallel processing may be added in the future using the message passing model.

Abstract: PURPOSE:To execute the processing smoothly at a high speed when the interruption occurs at the virtual computer by transferring a stack, obtaining the address of the interruption handler of the object virtual computer by a vector table and shifting the control, when the interruption is detected by a discriminating device. CONSTITUTION:When some requests are executed from a computer VM (2-1-2-n), the control is shifted through a VM supporting function 5 realized on the hardware to a virtual computer control program VMCP1-1. The program VMCP1-1 sets the discrimination whether the interruption is executed or not, to a hard register 20, starting is controlled by the starting control function 5-1 of the computer VM provided in the function 5, and in case of interruption, the control is shifted to an interruption handler and except it, the control is shifted to the next instruction of the computer VM. Thus, the interruption processing can be executed at a high speed and smoothly.

Abstract: PURPOSE: To attain the proper allocation of a real processor in response to the level and change of the load of a virtual processor, by eliminating the limitation for allocation of the real processor to the virtual processor. CONSTITUTION: It is supposed that a virtual processor corresponding to a certain VP state table is running on a processor 2 and a certain area of the address space of the virtual processor is locked by another virtual processor of the same VM. Thus a lock deciding instruction is produced for check whether said area is locked by another processor or not for the OS on the running virtual processor. Then the arithmetic code of said instruction is set to an arithmetic code register 71 and the conditional code is formed at a conditional code register 72 to show that a subject area is locked. Here comparators 143 and 144 produce coincidence signals respectively and an AND circuit 145 outputs the signal to a line 102 in response to those coincidence signals to start a processor state saving mechanism 13. Then the mechanism 13 shifts the control to a dispatch instruction group 6. COPYRIGHT: (C)1987,JPO&Japio

Abstract: PURPOSE: To reduce an overhead by selecting and starting a virtual processor that is run next based on the running priority designated by a VMCP CONSTITUTION: A PSW 8 is set under a waiting state by an OS on a running virtual processor In other words, an instruction which sets a wait bit 9 at '1' is outputted to an instruction executing circuit 4 via a line 100 Thus the bit 9 of the PSW 8 is set at '1' via a line 101 in case said instruction can be executed directly by the circuit 4 and an instruction executing microprogram 12 Then a virtual processor state saving mechanism 10 is started by a line 102 to save the state of a virtual processor together with a virtual processor state saving microprogram 11 Thus it is possible to drive the virtual processor that satisfies the running conditions with an inactive processors excepting for the corresponding processor COPYRIGHT: (C)1987,JPO&Japio

Abstract: An editing system for use in a virtual machine environment in which two virtual machines (102, 104) having corresponding virtual storage areas are operatively related to one another. The editing system allows a first virtual machine (102) to print, display, modify and otherwise control and process information stored in a second virtual machine (104) storage area.

Abstract: PURPOSE:To perform the input/output processing of a virtual computer at a high speed by applying a virtual input/output system not only to a virtual disk produced temporarily but to a magnetic disk device containing a permanent file. CONSTITUTION:A control table 54 is produced in response to the address of a virtual device described to a VDISKF. Then a has table 57 needed for conversion into a virtual address to a CCHHR is secured together with a synonym table 58. The addresses of these tables are set within the table 54. At the same time, a virtual memory space is produced and its segment address is also set on the table 54. A buffer equivalent to the track length is secured in order to read out the record on a real disk for each track. Then zero is set as the initial value of the virtual address. This virtual address is replaced by adding the length of both key and data parts of each record together as the record is read into a virtual disk space.