Topic
Video Graphics Array
About: Video Graphics Array is a research topic. Over the lifetime, 1962 publications have been published within this topic receiving 13988 citations. The topic is also known as: VGA.
Papers published on a yearly basis
Papers
TL;DR: A 1 k-pixel camera chip for active terahertz video recording at room-temperature has been fully integrated in a 65-nm CMOS bulk process technology and includes row and column select and integrate-and-dump circuitry capable of capturing terAhertz videos up to 500 fps.
Abstract: A 1 k-pixel camera chip for active terahertz video recording at room-temperature has been fully integrated in a 65-nm CMOS bulk process technology. The 32 × 32 pixel array consists of 1024 differential on-chip ring antennas coupled to NMOS direct detectors operated well-beyond their cutoff frequency based on the principle of distributed resistive self-mixing. It includes row and column select and integrate-and-dump circuitry capable of capturing terahertz videos up to 500 fps. The camera chip has been packaged together with a 41.7-dBi silicon lens (measured at 856 GHz) in a 5 × 5 × 3 cm3 camera module. It is designed for continuous-wave illumination (no lock-in technique required). In this video-mode the camera operates up to 500 fps. At 856 GHz it achieves a responsivity Rv of about 115 kV/W (incl. a 5-dB VGA gain) and a total noise equivalent power (NEPtotal) of about 12 nW integrated over its 500-kHz video bandwidth. At a 5-kHz chopping frequency (non-video mode) a single pixel can provide a maximum responsivity Rv of 140 kV/W (incl. a 5-dB VGA gain) and a minimum noise equivalent power ( NEP) of 100 pW/√Hz at 856 GHz. The wide-band antenna and pixel design achieves a 3-dB bandwidth of at least 790-960 GHz.
431 citations
TL;DR: Neurolucida is a new software package for performing 3-D neuron mapping and tracing to 0.5 micron precision through the oculars of a microscope and has a video mode compatible with frame grabbers, thereby permitting its application to video microscopy.
226 citations
TL;DR: In this paper, the authors describe an all CMOS variable gain amplifier (VGA) suitable for use in disk drive read channels, which maintains a 3 dB bandwidth greater than 85 MHz throughout its gain range.
Abstract: We describe an all CMOS variable gain amplifier (VGA) suitable for use in disk drive read channels. The VGA maintains a 3 dB bandwidth greater than 85 MHz throughout its gain range. This ensures good phase linearity for data transfer rates of up to 50 Mb/s. The VGA provides a 25 db gain variation along an ideal exponential gain to control voltage curve and 30 dB of gain control if ideal exponential characteristics is not absolutely necessary. The VGA achieves the necessary exponential gain to control voltage characteristics intrinsically using only MOS transistors as a single unit to reduce power and area consumption. Overall power consumption is less than 10 mW for the VGA circuit excluding the off-chip buffer circuits. >
220 citations
1 Feb 2017
TL;DR: A 640×480 VGA-resolution DVS system with a 9µm pixel pitch supporting a data rate of 300Meps for sufficient event transfer in spite of higher resolution is reported.
Abstract: We report a VGA dynamic vision sensor (DVS) with a 9µm pixel, developed through a digital as well as an analog implementation. DVS systems in the literature try to increase spatial resolution up to QVGA [1–2] and data rates up to 50 million events per second (Meps) (self-acknowledged) [3], but they are still inadequate for high-performance applications such as gesture recognition, drones, automotive, etc. Moreover, the smallest reported pixel of 18.5µm is too large for economical mass production [3]. This paper reports a 640×480 VGA-resolution DVS system with a 9µm pixel pitch supporting a data rate of 300Meps for sufficient event transfer in spite of higher resolution. Maintaining acceptable pixel performance, the pixel circuitry is carefully designed and optimized using a BSI CIS process. To acquire data (i.e., pixel events) at high speed even with high resolution (e.g., VGA), a fully synthesized word-serial group address-event representation (G-AER) is implemented, which handles massive events in parallel by binding neighboring 8 pixels into a group. In addition, a 10b programmable bias generator dedicated to a DVS system provides easy controllability of pixel biases and event thresholds.
208 citations
Patent•
20 Dec 2000
TL;DR: In this article, a bank pair is cross-coupled in parallel, the IF signal is applied to the bank pair decoupled from a control signal used to control transconductance output gain of the bank pairs over a range of input voltages, and a digital IF demodulator is disposed on the substrate and coupled to the VGA for low voltage applications, for converting theIF signal to a demodulated baseband signal.
Abstract: An integrated communications system. Comprising a substrate having a receiver disposed on the substrate for converting a received signal to an IF signal. Coupled to a VGA for low voltage applications and coupled to the receiver for processing the IF signal. The VGA includes a bank pair having a first bank of differential pairs of transistors and a second bank of differential pairs of transistors. The bank pair is cross-coupled in parallel, the IF signal is applied to the bank pair decoupled from a control signal used to control transconductance output gain of the bank pair over a range of input voltages. A digital IF demodulator is disposed on the substrate and coupled to the VGA for low voltage applications, for converting the IF signal to a demodulated baseband signal. And a transmitter is disposed on the substrate operating in cooperation with the receiver to establish a two way communications path.
207 citations
Related Topics (5)
Performance Metrics
| Year | Papers |
|---|---|
| 2026 | 1 |
| 2025 | 7 |
| 2024 | 17 |
| 2023 | 68 |
| 2022 | 74 |
| 2021 | 18 |