About: Video display controller is a research topic. Over the lifetime, 79 publications have been published within this topic receiving 1040 citations. The topic is also known as: VDC & display interface.
TL;DR: In this article, a wagering device video display system for displaying a presentation on a plurality of display devices is presented, where each video display may be controlled by a video display controller that is adapted to communicate with other video display controllers.
Abstract: A wagering device video display system for displaying a presentation on a plurality of display devices. A plurality of gaming devices and video displays are provided. Each video display may be controlled by a video display controller that is adapted to communicate with other video display controllers. When a multi-screen presentation is requested by a gaming device or a game device controller, the video display controllers coordinate among themselves to determine when the presentation will be displayed. Various bonus presentations or attractive presentations may be displayed on a plurality of video screens.
TL;DR: The use of video/audio signal streams such as in the past have been distributed by broadcast over radio frequency bands or by cable distribution, or made available from video recorder/player devices such as cassette recorders or video disc players.
Abstract: The use of video/audio signal streams such as in the past have been distributed by broadcast over radio frequency bands or by cable distribution, or made available from video recorder/player devices such as cassette recorders or video disc players, or made available from direct, live sources such as cameras, game systems or computers. In accordance with this invention, programs stored in memory devices associated with microcontrollers controlling the display to a user are constructed in a language which uses layered statements, each of which can have a description portion, an action portion, and a unique connecting character.
TL;DR: In this paper, a video display controller consisting of an image data read circuit which reads the image data from a video RAM, a register into which data representative of amount of shift of the video image is stored by a central processing unit, and a first counter which cyclicly counts a clock signal.
Abstract: There is provided a video display controller which can vertically and horizontally shift a whole video image displayed on a screen of a video display unit. The video display controller comprises an image data read circuit which reads the image data from a video RAM, a register into which data representative of amount of shift of the video image is stored by a central processing unit, and a first counter which cyclicly counts a clock signal. An adder adds the data contained in the register and a count output of the first counter, and at a timing determined by this addition result a predetermined value is preset into a second counter. This second counter counts the clock signal from the predetermined value, and the image data read by the image data read circuit is outputted to the video display unit at a timing in accordance with a count output of this second counter. The register, first counter, adder and second counter are provided in each of vertical and horizontal scanning control circuits.
TL;DR: In this article, a power saving controller implementing one of several available power saving modes dependent upon one or more of several possible inputs is presented. Each of the power-saving modes includes the same list of VDC functions which may individually be enabled or disabled in each power saving mode dependent upon a bit value entered into a register of the VDC.
Abstract: A computer system includes an operator input device, a central processing unit (CPU), and a display device, such as a liquid crystal display (LCD) or cathode ray tube (CRT) providing a visible image to the computer user as an output of computer activity. The computer system includes a video display controller (VDC) with a graphics generator. This VDC receives image information, such as text or graphics generated by the CPU, or retrieved by the CPU from another facility (such as a CD-ROM) of the computer system, and responsively provides image signals driving the CRT or LCD display. The VDC includes a power saving controller implementing one of several available power saving modes dependent upon one or more of several possible inputs. Each of the power saving modes includes the same list of VDC functions which may individually be enabled or disabled in each power saving mode dependent upon a bit value entered into a register of the power saving controller. Each of the power saving modes is ranked with the others in an order of succession. Accordingly, when each mode of power saving is enabled, it disables the lower-ranked modes of power saving. In turn, each mode of power saving is disabled and succeeded if a higher-ranked mode is enabled.
TL;DR: In this paper, a display data processing circuit (DDPC) is proposed to decode bit-words from a first-in-first-out (FIFO) memory to a second-bit-word format as required by a particular one of the display devices.
Abstract: A computer system includes a pair of display devices, such as cathode ray tubes (CRT's) or liquid crystal displays (LCD's) for providing a visible display to a user of the computer system. The computer system includes a video display controller (VDC) providing for simultaneous display of different images on the pair of display devices. The VDC includes a display data processing circuit (DDPC) which is variably configurable to provide decoding of data words from a first bit-word format as received from a display first-in-first-out (FIFO) memory to a second bit-word format as required by a particular one of the pair of display devices. The DDPC is variably configurable to allow the pair of display devices to each receive driving signals providing the simultaneous differing images, and which driving signals originate with the bit-words allocated to each particular one of the pair of display devices. Accordingly, the DDPC simultaneously decodes bit-words from the first bit-word format to a pair of second bit-word formats, which second bit-word formats need not be the same, but can differ depending on the type of display device receiving the corresponding driving signals.