Verilog Procedural Interface

Abstract: Designing a mixed-signal integrated hardware requires the mixed simulation for legacy digital blocks and analog circuits, which are usually represented by the Verilog description language for digital blocks and the SPICE circuit netlist of analog circuits Without model translations or source-level modifications and to simulate mixed legacy Verilog models and SPICE circuit netlists that are usually developed based on the different SPICE languages, parameters and primitives, this paper proposes a simulation framework whose concept is connecting a legacy Verilog and proper SPICE simulator for the target SPICE model using a run-time infrastructure (RTI) based on high level architecture (HLA) and adapters that are pluggable libraries to enable the interoperation and integration of simulators through HLA For the interoperation, to exchange analog/digital signals, the adapter converts analog/digital signals to events or events to analog/digital signals using user-defined, signal-event converters To synchronize different time advance policies, the adapter performs time synchronization procedures based on the pre-simulation concept For the integration of Verilog/SPICE simulators and the RTI, adapters are developed following each component interface, which are IEEE-std Verilog procedural interface, proposed SPICE procedural interface and IEEE-std HLA interface The proposed framework was applied to the digitally controlled buck converter simulation

Abstract: As an alternative to traditional fault injection-based methodologies and to explore the applicability of modern machine learning algorithms in the field of reliability engineering, this paper proposes a systemic framework that explores gate-level netlist circuit abstractions to extract and exploit relevant feature representations in a low-dimensional vector space. A scalable feature learning method on a graphical domain called node2vec algorithm [6] had been utilized for efficiently extracting structural features of the netlist, providing a valuable database to exercise a selection of machine learning (ML) or deep learning (DL) algorithms aiming at predicting fault propagation metrics. The current work proposes to model the gate-level netlist as a Probabilistic Bayesian Graph (PGB) in the form of a Graph Modeling Language (GML) format. To accomplish this goal, a Verilog Procedural Interface (VPI) library linked to standard simulation tools has been built to map gate-level netlist into the graph model. The extracted features have used for predicting the Functional Derating (FDR) factors of individual flip-flops of a given circuit through Support Vector Machine (SVM) and Deep Neural Network (DNN) algorithms. The results of the approach have been compared against data obtained through first-principles approaches. The whole experiment implemented on the features extracted from the 10-Gigabit Ethernet MAC IEEE 802.3 standard circuit.

Abstract: This paper presents a new test methodology which utilizes the programming language interface (PLI) for performing fault simulation of combinational or full scan intellectual property (IP) core-based designs for system-on-chip (SOC). Using the latest Verilog PLI, referred to as Verilog procedural interface (VPI), critical-path tracing and two-value deductive fault simulations are performed on a pre-compiled core basis as available in a simulator's intermediate format. By applying this VPI-based test methodology on ISCA S85 Verilog benchmarks results are presented in terms of elapsed simulation time and fault coverage for stuck-at faults and improvement over previous works is reported.