Abstract: Recent advances in technology have made low cost, low power wireless sensors a reality. Clock synchronization is an important service in any distributed system, including sensor network systems. Applications of clock synchronization in sensor networks include data integration in sensors, sensor reading fusion, TDMA medium access scheduling, and power mode energy saving. However, for a number of reasons, standard clock synchronization protocols are unsuitable for direct application in sensor networks. In this paper, we introduce the concept of adaptive clock synchronization based on the need of the application and the resource constraint in the sensor networks. We describe a probabilistic method for clock synchronization that uses the higher precision of receiver-to-receiver synchronization, as described in Reference Broadcast Synchronization (RBS) protocol. This deterministic protocol is extended to provide a probabilistic bound on the accuracy of the clock synchronization, allowing for a tradeo between accuracy and resource requirement. Expressions to convert service specifications (maximum clock synchronization error and confidence probability) to actual protocol parameters (minimum number of messages and synchronization overhead) are derived. Further, we extend this protocol for maintaining clock synchronization in a multihop network.

Abstract: Accurate, reliable timestamping which is also convenient and inexpensive is needed in many important areas including real-time network applications and network measurement. Recently the TSC register, which counts CPU cycles in popular PC architectures, was proposed as the basis of a new software clock which in terms of rate performance performs as well as more expensive GPS alternatives. Smooth and precise clock rate is essential to measure time differences accurately. We show how to define a TSC based clock which is also accurate with respect to absolute time. The clock is calibrated by processing, in a novel way, timestamps contained in the usual flow of Network Time Protocol (NTP) packets between a NTP server and the existing software clock, and TSC timestamps made independently on the host side. Using real measurements over 4 months, validated with a GPS synchronized hardware timing solution, the algorithm measured absolute time with a median error of only 30 microseconds when using a nearby stratum-1 NTP server. Results for two other servers are given. We also provide new algorithms for the robust determination of clock rate. We exploit the reliability of the available hardware to design synchronization algorithms which are inherently robust to many factors including packet loss, server outages, route changes, temperature environment, and network congestion.

Abstract: In this article we examine the problem of synchronizing the time-of-day clock in one node of an automation network system with a reference clock. The emphasis of this article is on switched, highly loaded networks, where unpredictable delays introduce excessive synchronization noise. PC clocks are accurate enough when connected within a network, but a new requirement is for them to be synchronized, which means that they should show the same time at the same instant. The most prominent time-synchronization method is the network time protocol proposed by Mills and Internet engineering task force group. A complete solution of the high-precision time-synchronization problem must reduce the randomness associated with the RTOS. The methods discussed in this article can help determine the frequency and time offset of a local time-of-day clock. The next challenge is to construct a local time-of-day clock and apply the synchronization information to it.

Abstract: Awareness of the need for robustness in distributed systems increases as distributed systems become an integral part of day-to-day systems. Tolerating Byzantine faults and possessing self-stabilizing features are sensible and important requirements of distributed systems in general, and of a fundamental task such as clock synchronization in particular. There are efficient solutions for Byzantine non-stabilizing clock synchronization as well as for non-Byzantine self-stabilizing clock synchronization. In contrast, current Byzantine self-stabilizing clock synchronization algorithms have exponential convergence time and are thus impractical. We present a linear time Byzantine self-stabilizing clock synchronization algorithm, which thus makes this task feasible. Our deterministic clock synchronization algorithm is based on the observation that all clock synchronization algorithms require events for re-synchronizing the clock values. These events usually need to happen synchronously at the different nodes. In these solutions this is fulfilled or aided by having the clocks initially close to each other and thus the actual clock values can be used for synchronizing the events. This implies that clock values cannot differ arbitrarily, which necessarily renders these solutions to be non-stabilizing. Our scheme suggests using a tight pulse synchronization that is uncorrelated to the actual clock values. The synchronized pulses are used as the events for re-synchronizing the clock values.

Abstract: An automated and configurable technique for runtime safety analysis of multithreaded programs is presented, which is able to predict safety violations from successful executions. Based on a user provided safety formal specification, the program is automatically instrumented to emit relevant state update events to an observer, which further checks them against the safety specification. The events are stamped with dynamic vector clocks, enabling the observer to infer a causal partial order on the state updates. All event traces that are consistent with this partial order, including the actual execution trace, are analyzed on-line and in parallel, and a warning is issued whenever there is a trace violating the specification. This technique can be therefore seen as a bridge between testing and model checking. To further increase scalability, a window in the state space can be specified, allowing the observer to infer the most probable runs. If the size of the window is 1 then only the received execution trace is analyzed, like in testing; if the size of the window is ∞ then all the execution traces are analyzed, such as in model checking.

Abstract: Described are approaches to routing buffered reference clock signals to a plurality of input/output (I/O) cell instances on an integrated circuit (IC) die. All or a subset of the I/O cell instances include clock routing resources optimized to deliver high-speed, low jitter clock signals within and through the particular instance. The clock routing resources in physically adjacent instances of the input/output cells for a given IC die automatically interconnect, collectively forming clock routing infrastructure optimized for groups of cell instances. This modular approach to clock routing simplifies the task of combining I/O cell instances with other I/O cell instances and with other types of circuitry.

Abstract: A method for low power clock tree synthesis using buffer insertion, removal and resizing for high-speed VLSI design is proposed. A developed tool can be embedded in the existing clock tree synthesis design flow to ensure satisfying both specifying database constrains and clock skew constrains. For a given clock tree netlist, location information of buffers, parameters of wires and buffers' timing and power library are all included. Buffer delay and wire delay of the given clock tree netlist are calculated first. Then, a feasible solution is solved if an input netlist is not feasible for given constrains. Finally, a modified low power clock tree netlist, which satisfies timing specifications, is obtained using the proposed method.

Abstract: This paper proposes the integration of internal and external clock synchronization by a combination of a fault-tolerant distributed algorithm for clock state correction with a central algorithm for clock rate correction. By means of hardware and simulation experiments it is shown that this combination improves the precision of the global time base in a distributed single cluster system while reducing the need for high-quality oscillators. Simulation results have shown that the rate-correction algorithm contributes not only in the internal clock synchronization of a single cluster system, but it can be used for external clock synchronization of a multi-cluster system with a reference clock. Therefore, deployment of the rate-correction algorithm integrates internal and external clock synchronization in one mechanism. Experimental results show that a failure in the clock rate correction does not hinder the distributed fault-tolerant clock state synchronization algorithm, since the state correction operates independently from the rate correction. The paper introduces new algorithms and presents experimental results on the achieved improvements in the precision measured in a time-triggered system. Results of simulation experiments of the new algorithms in single-cluster and multi-cluster configurations are also presented.

Abstract: A method and apparatus for processing packetized data spanning multiple clock cycles includes at least one comparator, for comparing a present clock cycle count to a reference clock cycle count, wherein the reference clock cycle values may be anywhere within the packet and may be non-contiguous with other reference clock cycle values. At least one word recognizer, compares a presently clocked word to a reference word, and an output circuit provides an indication of a favorable word comparison that occurred in response to a favorable clock cycle count comparison.

Abstract: A method of providing a secure clock in a communication device in contact with a communication system includes detecting a clock event whenever a clock event occurs; initializing a secure clock and setting a secure clock flag to TRUE; and setting the secure clock to a secure clock time. A secure clock mechanism for use in a communication device which is in contact with a communication system includes real-time clock hardware; programmable memory and non-volatile memory; and a back-up battery for powering the secure clock mechanism; a clock event detection mechanism for detecting clock events, which are taken from a group of clock events consisting of user clock events and system clock events; a secure clock initializing mechanism for setting the secure clock and for setting a secure clock flag to TRUE; and a secure clock setting mechainism for setting the secure clock to a secure clock time.

Abstract: A system receives multiple data samples and determines time stamp values associated with each of the multiple data samples. The system identifies an earliest time stamp value and uses that time stamp value as an initial system clock value. The system may also subtract a delay factor from the earliest time stamp value to account for delay in decoding the multiple data samples. The earliest time stamp value is also communicated to an audio decoder and a video decoder. The audio and video decoders provide clock data back to a component that maintains the system clock value. If the difference between the clock data received from the decoders and the system clock value exceeds a threshold value, the system clock value is recalculated.

Abstract: A technique is provided for simultaneous and/or selective self-testing of internal logic and asynchronous boundaries of an IC having a plurality of clock domains. A clock command is generated by an on product clock generator for each clock domain simultaneously; and an asynchronous receive clock driver provides a programmable delay to a capture clock based on predetermined cycle requirements of the asynchronous boundaries. Asynchronous boundary test requirements are defined exclusively from the perspective of the asynchronous boundary receiver latches, thereby reducing dependencies among clock domains. Advantageously, the design of internal logic and asynchronous boundaries of each clock domain, ultimately residing within an IC, can proceed without a priori knowledge of how the clock domain will eventually be used in aggregation with other clock domains.

Abstract: A method and apparatus for rapidly selecting types of buffers which are inserted in the clock tree for high-speed VLSI design is disclosed. The developed tool can be embedded in the existing clock tree synthesis design flow to ensure minimizing the clock delay and satisfying the clock skew constrains. Given the clock tree netlist, the inserted buffers location information, the wire electrical parameters and a buffers timing library, the components delay (buffer delay and wire delay) of the clock tree can be calculated first. Then, for each I/O pin, the path delay, the clock delay and the clock skew can be obtained. Finally, using the method, a modified clock tree netlist satisfying the timing specifications can be constructed.

Abstract: Having small-sized logical clocks with high causal-ordering accuracy is useful, especially where (i) the precision of the knowledge of the causal dependencies among events implies savings in time overhead and (ii) the cost of transmitting full vector clock timestamps - that precisely characterise the causal relation - is high. Plausible clocks can be used as timestamps to order events in a distributed system in a way that is consistent with the causal order as long as the events are causally dependent. We introduce the nonuniformly mapped R-entries vector (NUREV) clocks, a general class of plausible clocks that allow accuracy adaptation and we analyse the ways that these clocks may relate causally independent event pairs. Our analysis resulted in a set of conclusions and the formulation of new, adaptive plausible clocks algorithms, with improved accuracy, even when the number of clock entries is very small, which is important in peer-to-peer communication systems.

Abstract: A method of providing a secure clock in a communication device in contact with a communication system includes detecting a clock event whenever a clock event occurs; initializing a secure clock and setting a secure clock flag to TRUE; and setting the secure clock to a secure clock time. A secure clock mechanism for use in a communication device which is in contact with a communication system includes real-time clock hardware; programmable memory and non-volatile memory; and a back-up battery for powering the secure clock mechanism; a clock event detection mechanism for detecting clock events, which are taken from a group of clock events consisting of user clock events and system clock events; a secure clock initializing mechanism for setting the secure clock and for setting a secure clock flag to TRUE; and a secure clock setting mechainism for setting the secure clock to a secure clock time.

Abstract: A hierarchal block for an IC includes a plurality of sequential registers, a plurality of clock buffers, and a plurality of clock pins (fig. 5-13). The sequential registers are grouped into a plurality of clusters (fig. 5-13). Each of the clock buffers is associated with a respective one of the clusters such that a clock net connection can be made beatween each clock pins and the respective one of the clock buffers (fig. 5-13).

Abstract: The invention relates to a method and an apparatus synchronizing clocks of network nodes in a communication network (8). An apparatus for synchronizing clocks of network nodes (10) in a communication network (8) comprises time selection means (1) adapted for comparing a priority assigned to a clock of a first node to a priority assigned to a clock of a second node and, based on the result of the comparison of the priorities, for determining a reference clock having a superior priority and a dependent clock having an inferior priority from the clocks of the first and second node; and clock management means (2) adapted for setting the time of the dependent clock to the time indicated by the reference clock.

Abstract: Large number of peer processes distributed in various types of networks are cooperating to achieve some objectives. The vector clock cannot be adopted to a scalable group due to the message length O(n) for number n of processes. A group is composed of local subgroups in each of which processes are in a local or personal area network and which are interconnected in a wide-area network. Processes in local subgroups use physical and linear clocks while processes in a wide-area network adopt vector clock. We discuss how to causally deliver messages by using local synchronization mechanisms of each subgroup. We evaluate the protocol in terms of number of messages ordered.

Abstract: The present invention provides an asynchronous FIFO apparatus and method for passing data between a first clock domain and a second clock domain of a data processing apparatus, the first clock domain being asynchronous with respect to the second clock domain. The asynchronous FIFO apparatus comprises a main FIFO memory operable to store the data to be passed between the first and second clock domains, the main FIFO memory being accessible from each clock domain under the control of an access pointer associated with that clock domain. For one or both of the clock domains, the amount of data accessible per clock cycle is variable. An auxiliary FIFO memory is also provided associated with each clock domain in which the amount of data accessible per clock cycle is variable, this auxiliary FIFO memory being operable to store the access pointer used to access the main FIFO memory from its associated clock domain, and the access pointer being stored at a location of the auxiliary FIFO memory specified by an auxiliary access pointer. Routing logic is then operable to pass the auxiliary access pointer to the other clock domain to enable that other clock domain to retrieve the access pointer stored in the auxiliary FIFO memory. This provides an efficient technique for enabling data to be passed between two asynchronous clock domains in situations where for at least one of the clock domains the amount of data accessible per clock cycle in the main FIFO memory is variable.

Abstract: An output clock is provided by a logic module and at least one flip-flop based on a reference clock. Each flip-flop receives the reference clock at a corresponding clock end and changes a signal level outputted at a corresponding output port according to rising or falling edges within each period of the reference clock. The logic module performs a logic operation among signals at each output port of the flip-flops to generate the output clock synchronized with the reference clock. Thereafter the output clock can be outputted through the data path provided by the logic module, and additional logical operations can be performed between the output clock and other signals.

Abstract: PROBLEM TO BE SOLVED: To provide a method, an apparatus, a system and a product to maintain a virtual real-time clock (vRTC) in a computer system that is logically partitioned. SOLUTION: A change for a hardware real-time clock (hRTC), which is performed while a partition manager is not operating (or is not in the state that it operates enough) is traced. Such a cumulative effect of the change for hRTC values can be acquired as a clock delta variable. Depending on an embodiment, while the partition manager is not executed, the change for hRTC is traced and a service processor can be structured so that the clock delta is generated. After loading, the partition manager can adjust vRTC using the acquired clock delta for preserving maintainability of vRTC by compensating the change for hRTC, which is performed while the partition manager is not executed. COPYRIGHT: (C)2005,JPO&NCIPI

Abstract: A scheduler includes: a schedule information acquisition section configured to acquire the number of first clock cycles and the number of second clock cycles as schedule information of a function belonging to a lower-hierarchy, the number of the first clock cycles being the number of clock cycles after an execution of the function is started until an input data of the function is used, the number of the second clock cycles being the number of clock cycles after an output data of the function is outputted until the execution of the function is completed; and a scheduling processing section configured to obtain operations executable in the first clock cycles and operations executable in the second clock cycles from among operations belonging to an upper-hierarchy for calling the function, based on the acquired schedule information, and to schedule the upper-hierarchy ensure that the obtained operations execute in parallel with the function.

Abstract: A method for time synchronisation of at least two clocks contained in a multiprocessor system, wherein a first clock having a predetermined clock rate generates consecutive respective time-stamps indicating the time and at least one second clock which has an adjustable clock rate is synchronised with the first clock at certain time intervals. At predetermined time intervals the relative temporal position of flanks of the first clock and of the second clock representing the transition between two consecutive time-stamps is recorded. From the change in the relative temporal position of the transition flanks of the first clock and of the second clock a correction factor representing the time deviation between the first clock and the second clock is determined. Using the correction factor representing the time deviation between the first clock and the second clock the clock rate of the second clock is readjusted in the sense of a diminution of the time deviation between the first clock and the second clock. The recording, determination and readjustment are repeated.

Abstract: Method, system and base station for providing time synchronisation between local clocks located in nodes within a network and a central clock. The proposed invention allows for a more precise time synchronisation to take place in a simple and cost effective manner between a central unit and at least two remote units, without having to modify the transport infrastructure of the system. The central unit upon reception of a global time from a network clock will update, its respective local clock. It will then calculate a regularity of reception of the global time and then schedule the transmission of clock synchronisation messages to the remote units, which in turn on reception of the clock synchronisation messages will update their local clocks.

Abstract: This paper addresses the effects of time borrowing and clock skew scheduling on level-sensitive synchronous circuits. Synchronization of level-sensitive circuits can be accomplished through single-phase or multi-phase clocking schemes. This paper expands previous single-phase clock signal analysis to include multiphase clock signal synchronization. The tradeoffs of synchronous circuit operation with different types of registers and synchronization schemes are analyzed. The presented timing analysis problem specifically targets clock period minimization. The modified big M method is used to linearize the formulation of the timing analysis problem and experiments are performed on the ISCAS'89 benchmark circuits. For single and multi-phase level-sensitive circuits, up to 63% and 62% improvements, respectively, over conventional zero-skew, flip-flop based circuits are achieved through the simultaneous application of both time borrowing and non-zero clock skew scheduling.

Abstract: Techniques are presented for creating a second clock signal by using a first clock signal. For instance, an output is determined that corresponds to a phase relationship between the first and second clock signals. A value, corresponding to a given one of a plurality of delays, is selected based at least partially on the output. The given delay is created, by using the value, on the first clock signal to produce the second clock signal, whereby the given delay creates a phase shift between the first and second clock signals.

Abstract: Owing to the asymmetry of Internet paths, more and more studies have turned to the measurement for one-way metrics. However, since the clocks at end systems often behave diversely, the synchronization between the end hosts is what we care about all along. In this paper, we firstly propose a general model for clock skew estimation in one-way measurements, which turns the problem of clock skew estimation to the solution of n-dimension equation group, and give the equation group what it needs based on different presumptions. We then present a Piece-wise Reliable Clock Skew Estimation Algorithm (PRCSEA), which introduces the reliability test of estimation results and eliminates the extra presumptions needed by other algorithms, such as only one clock adjustment in the measurements. PRCSEA solves the skew estimation problem in a heuristic way, and it can handle many special cases affecting the estimation of clock skew, such as routing change, clock hiccup and network congestion. PRCSEA is the only algorithm that can handle non-constant clock skew to the best of our knowledge. The time complexity of PRCSEA is O(n*logn), which is the same as that of Paxson's algorithm.

Abstract: A speculative transfer mechanism transfers a source synchronous read request from a first clock domain to a second clock domain. The address portion having address information is transferred to the second clock domain in response to detecting a source synchronous address strobe latching signal. A pointer is generated in response to detecting the address strobe latching signal and passed into the second clock domain. In one embodiment, a pointer is retimed to be stable for a timing window for which a crossover of the address portion may be performed in the second clock domain. Request logic in the second clock domain generates a read command based on the address portion and the pointer.