Abstract: Awareness of the need for robustness in distributed systems increases as distributed systems become an integral part of day-to-day systems. Tolerating Byzantine faults and possessing self-stabilizing features are sensible and important requirements of distributed systems in general, and of a fundamental task such as clock synchronization in particular. There are efficient solutions for Byzantine non-stabilizing clock synchronization as well as for non-Byzantine self-stabilizing clock synchronization. In contrast, current Byzantine self-stabilizing clock synchronization algorithms have exponential convergence time and are thus impractical. We present a linear time Byzantine self-stabilizing clock synchronization algorithm, which thus makes this task feasible. Our deterministic clock synchronization algorithm is based on the observation that all clock synchronization algorithms require events for re-synchronizing the clock values. These events usually need to happen synchronously at the different nodes. In these solutions this is fulfilled or aided by having the clocks initially close to each other and thus the actual clock values can be used for synchronizing the events. This implies that clock values cannot differ arbitrarily, which necessarily renders these solutions to be non-stabilizing. Our scheme suggests using a tight pulse synchronization that is uncorrelated to the actual clock values. The synchronized pulses are used as the events for re-synchronizing the clock values.

Abstract: The object of the present invention is to prevent an out-of-sync state of clocks from occurring in an IP network or an IP-based radio access network in which network fluctuation delays occur The synchronous server includes a clock generator 11 configured to periodically generate a clock and a synchronous message transmitter 14 and 15 configured to generate a synchronous message for notifying information regarding the generated clock, and to transmit the generated synchronous message to the node using an IP packet The node includes a time calculator 18 configured to obtain a time of receiving the synchronous message and a clock correction processor 20 configured to calculate a clock correction value in accordance with the time of receiving the synchronous message and the information regarding the clock notified by the synchronous message, and to correct a generated timing of a clock in the node in accordance with the clock correction value

Abstract: Methods, apparatus and computer readable medium are described that attempt increase trust in a wall time provided by a real time clock. In some embodiments, a detector detects activities that may be associated with attacks against the real time clock. Based upon whether the detector detects a possible attack against the real time clock, the computing device may determine whether or not to trust the wall time provided by the real time clock.

Abstract: The frequency of a local clock of a local data processor in communication with an asynchronous switched packet network is synchronized to the frequency of a reference clock of a source data processor also coupled to the network. Timing packets each including a field containing the destination address of the local processor and a field containing reference clock data indicating the time at which the packet is launched onto the network are sent to the local data processor from the source data processor across the network. The frequency of the local clock is controlled in dependence on the reference clock data and the times of arrival of the packets.

Abstract: Time synchronization is critical in distributed environments. A variety of network protocols, middleware and business applications rely on proper time synchronization across the computational infrastructure and depend on the clock accuracy. The ''network time protocol" (NTP) is the current widely accepted standard for synchronizing clocks over the Internet. NTP uses a hierarchical scheme in order to synchronize the clocks in the network. In this paper we present a novel non-hierarchical peer-to-peer approach for tune synchronization termed CTP - classless time protocol. This approach exploits convex optimization theory in order to evaluate the impact of each clock offset on the overall objective function. We define the clock offset problem as an optimization problem and derive its optimal solution. Based on the solution we develop a distributed protocol that can be implemented over a communication network and prove its convergence to the optimal clock offsets. For compatibility, the CTP may use the exact format and number of messages used by NTP. We also present methodology and numerical results for evaluating and comparing the accuracy of time synchronization schemes. We show that the CTP substantially outperforms hierarchical schemes such as NTP in the sense of clock accuracy with respect to a universal clock, without increasing complexity.

Abstract: The invention represents a parallel and distributed approach to clock recovery based on multiple mutually phase shifted sample clock signals (aS) defining a set of orthogonal clock phases. The phase shifted clock signals are used for obtaining an input data sample representation (aU). Input data transition detection is accomplished by determining, for each one of the above clock phases, whether input data samples within a detection window associated with the respective clock phase include an input data transition vector (I). A corresponding clock selection control signal vector (I) is generated based on the input data transition vector (I) to determine a clock selection master. In order to dynamically extract an output clock signal, to control signal vector (I) is then logically combined with a representation (aS'), preferably a rotated version, of the sample clock vector (aS).

Abstract: A design tool inserts randomized delays into synchronizers for signals crossing from one clock domain to another. Rather than having a wide range of random delays to select from, each synchronizer's randomized delay is selected from only two possibilities. An added delay of either zero or one clock period of the new domain's clock is added as the randomized delay. The randomized delay causes the re-synchronized domain-crossing signal to become available either in the expected cycle or in the cycle following the expected cycle. Logic hazards caused by the domain-crossing signal can be detected and the possible results simulated. The synchronizer can be a series of two flip-flops, with the random delay added to the first flip-flop. Randomized delays of either one or none added periods of the clock can also be added to multi-cycle signals within one clock domain that have two or more clock cycles to propagate.

Abstract: A method for calculating an estimate of the clock skew between a sender's clock and a receiver's clock in a packet-based communications network. An adaptive algorithm is employed in which a recursive least squares approach is used to calculate an estimate of the clock skew based on the transmission of a given (i e., the “current”) packet, which estimate is further based on a previous estimate thereof (“a first approximation” thereof). This illustrative process then iterates with each new packet, producing increasingly accurate estimates of the clock skew.

Abstract: System and method for providing clocks to digital circuitry with a need for multiple clocks. A preferred embodiment comprises an oscillator controller (oscillator clock domain block 305 ) distributes a system clock generated by an oscillator to a plurality of clock domain blocks (GSM clock domain block 310 and so forth). The clock domain blocks use the system clock to generate specific clocks needed by attached hardware. The clock domain blocks may be programmed after manufacture to permit customized clock generation to meet requirements.

Abstract: A method and apparatus for transferring data across a clock domain boundary is described. In one embodiment, a fixed relationship between a faster clock and a slower clock is maintained in the process of phase alignment to allow great flexibility in allowable combinations of slower clock and faster clock frequencies. In one embodiment, an encoded edge select word is generated once at system initialization and used thereafter to select edges of the faster clock on which to sample data that comes from the clock domain of the slower clock. The value of the encoded edge select word is based, in part, on the fixed relationship between the faster clock and the slower clock.

Abstract: Foundational and scalable techniques for runtime safety analysis of multithreaded programs are explored in this paper. A technique based on vector clocks to extract the causal dependency order on s...

Abstract: Vector clocks are the appropriate mechanism used to track causality among the events produced by a distributed computation. Traditional implementations of vector clocks require application messages to piggyback a vector of n integers (where n is the number of processes). This paper investigates the tracking of the causality relation on a subset of events (namely, the events that are defined as "relevant" from the application point of view) in a context where communication channels are not required to be FIFO, and where there is no a priori information on the connectivity of the communication graph or the communication pattern. More specifically, the paper proposes a suite of simple and efficient implementations of vector clocks that address the reduction of the size of message timestamps, i.e., they do their best to have message timestamps whose size is less than n. The relevance of such a suite of protocols is twofold. From a practical side, it constitutes the core of an adaptive timestamping software layer that can used by underlying applications. From a theoretical side, it provides a comprehensive view that helps better understand distributed causality-tracking mechanisms.

Abstract: A system for determining a timing offset between a first clock and a second clock at respective first and second points in a communications network. A series of request signals is transmitted from the first point in the network to the second point in the network. A series of reply signals is transmitted from the second point in the network to the first point in the network. Each reply signal and a corresponding reply signal having a minimum round trip delay time are identified and a minimum single leg delay time is determined from the minimum round trip delay time. A timing offset between the clock values of the first clock and the second clock at a first instance is estimated, the estimation being based upon the minimum single leg delay time, and a transmission time and a reception time of one of the identified request signal and the corresponding reply signal, as given by the respective clocks at the transmission and reception points of the signal.

Abstract: It is known that the clock skew can be exploited as a manageable resource to improve the circuit performance. However, due to the limitation of race condition, the optimal clock skew scheduling does not achieve the lower bound of the clock period. In this paper, we propose a polynomial time complexity algorithm, which incorporates optimal clock skew scheduling and delay insertion, for the synthesis of non-zero clock skew circuits. The main advantages of our algorithm include two parts. First, it guarantees to achieve the lower bound of the clock period. Secondly, it also tries to minimize the required inserted delays under the lower bound of the clock period. Experimental data shows that, even though we only use the buffers in a standard cell library to implement the delay insertion, our approach still works well.

Abstract: Clock skew and clock distribution are increasingly becoming a major design concern in synchronous pipelined systems. We present a novel high-speed hybrid wave-pipelined linear feedback shift register that manages clock skew by permitting the clock to travel with its associated data through the pipeline. The wave-pipelined clock has a skew 8.34 times lower than that of a buffered clock and is 1.2 times faster.

Abstract: A method for recovering a service clock through a packet network for the provision of isochronous services uses a two-layer arrangement wherein stable oscillators are provided at the transmitting and receiving nodes. ACR is used to tune the local oscillators over a long period of time. SRTS is used to transfer the service clock except the timestamp information is based on the local oscillators at the transmitting and receiving nodes instead of the common network clock.

Abstract: An apparatus ( 21 ) is provided for recovering a reference clock generated by a master clock ( 22 ) in a sender ( 20 ). The sender ( 20 ) sends timing packets over a network ( 3 ). The apparatus comprises a controllable slave clock ( 27 ) and a control circuit ( 25, 26, 28 ) which determines the slave clock error and controls the slave clock ( 27 ) so as to reduce the error. The error is determined as a function of (m×N)−C a (n), where C a  ( n ) = ( ∑ i = 0 q - 1   C  ( n - i ) ) / q . N is the number of cycles of the master clock between the sending of consecutive timing information items, C(r) is the number of slave clock cycles between receipt of the (r−m)th and rth timing information items from the network, m is an integer greater than 0, and q is an integer greater than 1. The control circuit ( 25,26,28 ) may alternatively or additionally be arranged to apply a correction V adj (t) to the slave clock at regular intervals T adj , and be arranged to apply a gain parameter dependent on the frequency difference between the master clock ( 22 ) and the slave clock ( 27 ) to each correction.

Abstract: This research direction aims to develop and analyze algorithms to solve problems of communication and data sharing in highly dynamic distributed environments The term dynamic here encompasses many types of changes, including changing network topology, processor mobility, changing sets of participating client processes, a wide range of types of processor and network failures, and timing variations Constructing distributed applications for such environments is a difficult programming problem In practice, considerable effort is required to make applications resilient to changes in client requirements and to evolution of the underlying computing medium We focus our work on distributed services that provide useful guarantees and that make the construction of sophisticated distributed applications easier The properties we study include ordering and reliability guarantees for communication and coherence guarantees for data sharing To describe inherent limitations on what problems can be solved, and at what cost, the algorithmic results will be accompanied by lower bound and impossibility results One example of our approach is the new dynamic atomic shared-memory service for message-passing systems We formally specified the service and developed algorithms implementing the service A system implementation is under development The service is reconfigurable in the sense that the set of owners of data can be changed dynamically and concurrently with the ongoing read and write operations We proved the correctness of the implementation for arbitrary patterns of asynchrony and crashes, and we analyzed its performance conditioned on assumptions about timing and failures

Abstract: In 21st-Century VLSI design, clocking plays crucial roles for both performance and timing convergence. Due to their non-convex nature, optimal minimum-delay/area zero-skew wire-sizing problems have long been considered intractable. None of the existing approaches can guarantee optimality for general clock trees to the authors' best knowledge. In this paper, we present an e-optimal zero-skew wire-sizing algorithm, ClockTune, which guarantees zero-skew with delay and area within e distance to the optimal solutions in pseudo-polynomial time. Extensive experimental results show that our algorithm executes very efficiently in both runtime and memory usage. For example, ClockTune takes less than two minutes and 35MB memory to size an industrial clock tree with 3101 sink nodes within 2% to the optimal solution on a 533MHz Pentium III PC. Our algorithm can also be used to achieve useful clock skew to facilitate timing convergence and to incrementally adjust clock tree for design convergence and explore delay/power tradeoffs during design cycles. ClockTune is available on the web [13].

Abstract: Disclosed is a method for automatically detecting and selecting a time correction protocol and a time base, from among many possible protocols, in a master/slave clock system. A “self-teaching” feature is also disclosed, which includes a table stored at the slave clock containing data representative of characteristics, such as the relative frequency and spacing, of each one of numerous different time correction pulses that can be received by the slave clock from the master clock. Then, at a time of time correction, the slave clock selects the protocol most likely being used by the master clock, based on historical data. The time displayed by the slave clock is the then updated to match the time displayed by the master clock.

Abstract: A system and method that controls the start time of different clocks in different clock domains, each of which is controlling an I/O, provides that the first cycle of each time domain is within a predetermined timing delay of one another. Reset signals are pipelined across the clock domains such that all the clocks trigger at substantially the same time. The clock channels may be arranged logically and physically in n groups of m channels with delays associated with each n group according to the relative position of the n group within the sequence of the n groups.

Abstract: Under the present invention a real time clock circuit, within a set-top box, is provided with an internal clock generator for generating multiple clock signals. Once generated, a first clock signal is divided into an initial set of values representing time and optionally day/date intervals, and then communicated to a set of clock registers. The initial set of values can then be communicated (directly or via a set of DCR registers) to a display component within the set-top box. Updated clock signals are received by the set of DCR registers from an external source such as a satellite or the like thus making the clock very accurate, and are communicated to the display component. Similar to the initial set of values, the updated set of values could be communicated to the display component directly from the set of DCR registers, or via the set of clock registers.

Abstract: Within a computer automated tool, a method ( 400 ) of estimating an upper-bound of an operational frequency of at least a portion of a placed circuit design can include identifying ( 405 ) a clock source within the placed circuit design, wherein the clock source is associated with a clock domain, and determining ( 410 ) an initial routing of the clock domain. The method also can include determining ( 420 ) a minimum path slack corresponding to each connection of the clock domain. Connections of the clock domain which have a lowest minimum path slack can be marked ( 430 ). One or more marked connections which are not routed in delay mode can be identified and routed in delay mode ( 455 ) allowing sharing of routing resources by different nets.

Abstract: A method for providing a next clock edge value calculation includes obtaining a clock file data, calculating a next clock edge value using the clock file data, and generating an output file using the next clock edge value. A method for providing an nth clock edge value calculation includes obtaining a clock file data and an n value calculating an nth clock edge value using the clock file data and the n value, and generating an output file using the nth clock edge value.

Abstract: A data processing machine including a CPU which is configured to operate with an adjustable (variable) clock frequency. The clock frequency is adjusted in accordance with a clock change request signal. A plurality of clock change request signals have respective priority orders. A plurality of clock frequencies are prepared for the clock change request signals. When two or more clock change request signals are input, one of them is selected based on the priority order. The clock signal (clock frequency) to be applied to the CPU is changed in accordance with the selected clock change request signal. The data processing machine can adjust a timing for memory access to an optimal timing when the clock frequency is adjusted. The data processing machine can also deal with various clock frequency change requests.

Abstract: This paper presents an innovative strategy to synchronize all virtual clocks in asynchronous Internet environments. Our model is based on the architecture of one reference clock and many slave clocks communicating with each other over the Internet. The paper makes three major contributions to this research area. Firstly, one-way information transmission is applied to reduce traffic overhead on the Internet for the purpose of clock synchronization. Secondly, the slave nodes use local virtual time and the arrival timestamp, from the reference node, to create linear mathematical trend models and to retrieve the clock precision differences between reference clock and slave clocks. Finally, a fault-tolerant and self-adaptive model executed by each slave node based on the above linear trend model is created in order to ensure that the virtual clock is running normally, even when the link between the reference node and this slave node has crashed. We also present detailed simulations of this strategy and mathematical analysis on real Internet environments.

Abstract: Keeping distributed clocks closely synchronized is one of the basic requirements in wireless embedded applications. In the context of wireless applications, a clock synchronization protocol must tolerate message losses and should have a low communication overhead. The purpose of this paper is to present a clock synchronization protocol for distributed embedded systems in wireless environments. Our protocol adopts the master/slave structure based on a time transmission protocol and uses a drift correction algorithm for clock synchronization. The master node broadcasts synchronization messages through access point. The slave node estimates the master clock using the time transmission protocol and adjusts its virtual clock based on the continuous clock synchronization. Another advantage of the proposed protocol is that it uses a linear number of messages by transmitting one synchronization message in each resynchronization round and tolerates message losses. The protocol is implemented and tested in a Windows NT and a WinCE. Its measurements indicate that the PC node and PDAs can be kept synchronized within the deviation bound of 8 milliseconds.

Abstract: The present invention refers to a global clock system for clusters or networks of computers implemented entirely in hardware. The system uses a specifically designed hierarchical network to distribute clock pulses that are used to increment time counters in the cluster' nodes. In addition, this network enables any node of the cluster to send a reset signal to the other nodes so that all local time counters are initialized simultaneously and remain automatically synchronized afterwards. In this way, each processor in the cluster is able to obtain the value of the global clock whenever accessing its own local time counter. The reset signal is the only function that is implemented in software.

Abstract: Systems of and methods for processing data for communication between a sender and a receiver are described. In one embodiment, the phase of a first clock is used to select between first and second portions of data from the sender. The selected data is then synchronized, for communication to the receiver, to a second clock having a frequency which is an integer multiple of that of the first clock, wherein the integer multiple is two or more. The first and second portions of the data may be provided to the same output pins in this embodiment for communication to the receiver. In a second embodiment, first and second portions of data from the sender are clocked in using first and second edges, respectively, of a first clock. The first and second edges have a first polarity if a first pre-determined mode is in effect, and have a second polarity if a second pre-determined mode is in effect. Data derived from the clocked in data is then synchronized, for communication to the receiver, to a second clock. In a third embodiment, data from the sender is clocked in using a first clock. The clocked in data is then transformed responsive to a pre-determined mode selected from a plurality of possible modes. The transformed data is then synchronized, for communication to the receiver, to a second clock. In a fourth embodiment, a first clock is provided which is delayed relative to a second clock by a pre-determined amount. Data is then clocked out for communication to a receiver using the second clock, and clocked in for communication back to the sender using a third clock derived from the second clock. Data derived from the clocked in data is then synchronized to the first clock.