Abstract: A digital logic circuit, such as a FIFO memory includes pointers, or indicators, generated in two clock domains, between which information is transferred, to indicate a location in the digital logic circuit for transferring the information into or out of the digital logic circuit within either clock domain Each pointer is encoded with a “2-hot” encoded value within one of the clock domains The 2-hot encoded value of each pointer is sent to the other clock domain to synchronize the pointer to the other clock domain as well as to its original clock domain Within each clock domain, the pointer generated therein and the pointer received from the other clock domain are used to determine whether the information can be transferred into or out of the digital logic circuit

Abstract: Methods, systems and computer program products are provided for synchronizing clocks in a computer network. A first node clock is synchronized to a second node clock by establishing an initial value of a virtual second node clock at the first node. The initial value may be established based on the first node clock and a timing record received from the second node. A frequency bias adjustment factor is determined for the virtual second node clock based on a plurality of clock requests from the first node and a plurality of corresponding responses from the second node spaced apart in time. The responses from the second node include the timing record based on the second node clock. A time of the virtual second node clock is provided based on the frequency bias adjustment factor responsive to requests for the virtual second node clock at a time between requests.

Abstract: A method and apparatus are provided for performing need based synchronization of a time clock maintained by a computer system. A number of computer systems are connected to a network, such as the Internet. Each computer system synchronizes its time clock by accessing a time server via the network. The time server may service a large number of client computer systems for purposes of providing accurate time of day readings and may therefore be subject to substantial loading. Accordingly, in each client system, the time clock is synchronized at least twice, and an amount of drift in the time clock is determined based on the two or more synchronizations. The synchronization interval for future synchronizations of the clock or the specific time of the next synchronization is then determined based upon the amount of drift, such that the time clock of each client computer system is synchronized only when necessary, and such that the loading on the time server is reduced.

Abstract: Method to enable a local system time clock counter (STC) of a receiving recording device to lock to program clock reference (PCR) information comprised in a received real time sequence of information signal packets, such as MPEG2 Transport Stream packets. The method comprising determining the number of cycles between arrival of the first information signal packet and the arrival of the information signal packet comprising the first Program Clock Reference (PCR) information. This information is stored as an attribute of the stored sequence.

Abstract: A clock tree insertion method for distributing a clock signal in an integrated circuit design includes providing a physical design representative of the integrated circuit design, specifying a location for a root node of the clock tree in the physical design, constructing an array of buffers as the clock tree where the array of buffers is constructed to minimize the maximum insertion delay from the root node to the clock signal endpoints and to meet a predefined maximum insertion delay constraint, identifying locations in the clock tree where clock skew violations occur and correcting the clock skew violations by introducing delay at buffer locations in the clock tree having the fastest clock signal arrival times, and identifying locations in the clock tree where minimum insertion delay violations occur and correcting the minimum insertion delay violations by slowing down the arrival times of clock signal endpoints of the clock tree.

Abstract: A clock (12) is provided for synchronizing with a master time service (16). The clock (12) includes a microprocessor (18) configured to obtain time code data from the master time service (16), process the time code data, and initiate a time keeping function. The clock (12) further includes a time indicator (24) connected to the microprocessor (18). The time indicator (24) displays a time corresponding to the time code data.

Abstract: Clock skew modeling is important in the performance evaluation and prediction of clock distribution networks. This paper addresses the problem of statistical skew modeling for general clock distribution networks in the presence of process variations. The only available statistical skew model is not suitable for modeling the clock skews of general clock distribution networks in which clock paths are not identical. The old model is also too conservative for estimating the clock skew of a well-balanced clock network that has identical but strongly correlated clock paths (for instance, a well-balanced H-tree). In order to provide a more accurate and more general statistical skew model for general clock distributions, we propose a new approach to estimating the mean values and variances of both clock skews and the maximal clock delay of general clock distribution networks. Based on the new approach, a closed-form model is also obtained for well-balanced H-tree clock distribution networks. The paths delay correlation caused by the overlapped parts of path lengths is considered in the new approach, so the mean values and the variances of both clock skews and the maximal clock delay are accurately estimated for general clock distribution networks. This enables an accurate estimate of yields of both clock skew and maximal clock delay to be made for a general clock distribution network.

Abstract: A system and method for enabling a node, such as a mobile user terminal in a wireless communications network, such as an ad-hoc network, to effectively and efficiently determine a clock correction factor for its local clock relative to a local clock of at least one other node The node calculates a difference between the timing of the local clock of the node and the local clock of the other node based on the timing of signals transmitted between the node and the other node, and information pertaining to the transmission and reception of these signals by the node and the other node as indicated by the respective local clocks of the node and the other node The system and method further enables a plurality of nodes in an ad-hoc packet-switched communications network to calculate their respective local clock correction factors relative to the local clocks of their neighboring nodes in this manner with minimal message transmissions between the nodes, to reduce the amount of overhead in the network needed for such clock correcting operations

Abstract: The invention relates to a method for synchronizing a first clock C to a reference clock A, the first clock C being connected to said reference clock A via a processing unit B. The invention moreover relates to a processing unit B and to a synchronization system. In order to enable a synchronization of said first clock C to said reference clock A via said processing unti B, it is proposed that the processing unit B generates a correction message cmsg for the first clock C based on timestamps exchanged between the processing unit B and the reference clock A, which exchange of timestamps is triggered by clock pulses cclk received in the processing unit B from the first clock C.

Abstract: A method for recovering clock signals includes generating a media sync signal to synchronize processing of digital media, and generating a transmission reference clock signal to define a duration of a transaction through a packet-based data network. The media sync and transmission clock signals may have different frequency and phase. The media is sent to a slave node of the network. The media sync and transmission clock signals are correlated to generate phase correlation information, and the phase correlation information is also sent to the slave node. Accordingly, a relatively low cost and reliable clock recovery technique suitable for synchronizing media streams across a packet-based data network is disclosed.

Abstract: A technique synchronizes clock forwarded interface circuits of a multiprocessor system having a plurality of nodes interconnected by a hierarchical switch. Each node includes a plurality of agents coupled to a local switch over clock forwarded links attached to the interface circuits. The local switch includes a unique command port that interacts with the interface circuits to distribute clock forwarding synchronization messages among the agents of each node. These synchronization messages are used as start events that activate the clock forwarded interface circuits to thereby insure proper synchronous operation of these circuits.

Abstract: A phase alignment circuit in a serial transmitter aligns a parallel input data stream to a first transmission clock before conversion to a serial output data stream using a second transmission clock which is a multiple of the first transmission clock. The phase alignment circuit introduces less delay, i.e., the output of the phase alignment circuit lags the input of the phase alignment by a few number of clock cycles (e.g., less than 2 clock cycles). The phase alignment circuit demultiplexes the input data stream into a plurality of intermediate data streams using a plurality of multi-phase clocks referenced to a data clock and multiplexes the plurality of intermediate data streams using sequence signals referenced to the first transmission clock. The sequence signals are initialized according to a reset condition and at least one of the multi-phase clocks.

Abstract: The Time Warp synchronization protocol allows causality errors and then recovers from them with the assistance of a cancellation mechanism. Cancellation can cause the rollback of several other simulation objects that may trigger a cascading rollback situation where the rollback cycles back to the original simulation object. These cycles of rollback can cause the simulation to enter a unstable (or thrashing) state where little real forward simulation progress is achieved. To address this problem, knowledge of causal relations between events can be used during cancellation to avoid cascading rollbacks and to initiate early recovery operations from causality errors. In this paper, we describe a logical time representation for Time Warp simulations that is used to disseminate causality information. The new timestamp representation, called Total Clocks, has two components: (i) a virtual time component, and (ii) a vector of event counters similar to Vector clocks. The virtual time component provides a one dimensional global simulation time, and the vector of event counters records event processing rates by the simulation objects. This time representation allows us to disseminate causality information during event execution that can be used to allow early recovery during cancellation. We propose a cancellation mechanism using Total Clocks that avoids cascading rollbacks in Time Warp simulations that have FIFO communication channels.

Abstract: We present a solution to guarantee scalable causal ordering through matrix clocks in Message Oriented Middleware (MOM). This solution is based on a decomposition of the MOM in domains of causality, i.e. small groups of servers interconnected by router servers. We prove that, provided the domain interconnection graph has no cycles, global causal order on message delivery is guaranteed through purely local order (within domains). This allows the cost of matrix clocks maintenance to be kept linear, instead of quadratic, in the size of the application. We have implemented this algorithm in a MOM, and the performance measurements confirm the predictions.

Abstract: A system architecture and method are provided for synchronizing the slave clock of one or more resources with the master clock of a controller in a document processing system. The method includes: a) saving a value of the master clock ( 615 ); b) generating a discrete clock synchronization interrupt signal and distributing the interrupt signal to the resource(s) via the control bus ( 625 ); c) receiving the interrupt signal at each resource ( 630 ) and saving a value of the slave clock ( 640 ); d) sending a message to the controller via a network to request the value saved for the master clock ( 645 ); e) sending the value to the resource ( 660 ); f) receiving the value ( 665 ); and g) subtracting the value saved for the slave clock from the value saved for the master clock to determine an error value between the clocks ( 690 ) and using the error value in an adjustment algorithm to synchronize the slave clock with the master clock ( 695 ).

Abstract: Method for accounting for factors (such as temperature) causing systematic errors (time-varying or constant) in a clock, such as a clock used in a ranging receiver (for use with a positioning system such as the Global Positioning System), and a corresponding clock system (including a clock and a filter such as a Kalman filter) for providing clock time and error, used for example in a ranging receiver. The invention adds new state vector components to account for systematic error. The process update equation used in the navigation solution is accordingly extended to include the additional components of the state vector.

Abstract: Apparatus and method for generating a divided clock signal. A ring counter is provided with a sequence of output states. During steady-state operation, a different one of the output states is set at a first logical level and each of the remaining output states is set at a second logical level at each successive clock transition in a master clock signal. A gate network uses the respective logical levels of the output states to generate the divided clock signal. An error detection circuit outputs an error detection signal when a number of the output states at the first logical level is other than one, and proceeds to synchronously reset the ring counter when the error condition is detected. A programmable processor further asynchronously resets the ring counter in response to the error detection signal, as desired.

Abstract: We propose a self-stabilizing K-phase clock protocol which works on uniform tree networks (i.e. without any root). The protocol is self-stabilizing because it guarantees that eventually all clock valve variables will be synchronized and advance in the same value, no matter what the initial state is. It requires (Deg/sub u/+1)K states by processor u, where Deg/sub u/ is the degree of u; i.e., the number of neighbors that processor u has. The worst case stabilization time is D, where D is the diameter of the tree. This is the first universal protocol (i.e. working for any K), whose stabilization time does not depend on K. Moreover, it is the fastest of all the phase clock protocols with bounded memory.

Abstract: A method of scheduling a CPU in which a clock of the CPU is controlled depending upon the states of processes to reduce power consumption. The clock is controlled by substituting clock functions of an embedded system into a scheduler function, competing a wait time until a scheduling is completed with the sum of an execution time given for satisfying a real-time condition and an error range of a permissible error of a scheduling changing a clock state of a process depending on the compared result, calculating an elapsed time with respect to a difference between the changed scheduling clock and a scheduling clock before the change of clock to control the wait time Wk and setting the clock of the CPU using the value of a newly determined clock.

Abstract: In this paper, we propose a new clock tree synthesis method for semi-synchronous circuits. A clock tree obtained by the proposed method is a multi-level multi-way clock tree such that a clock-input timing of each register is a multiple of a predefined unit delay and the length of interconnection from a parent node to its child is upper bounded. The clock trees are constructed for several practical circuits. The size of each clock tree is comparable to a zero skew clock tree. In order to assure the practical quality, they are examined under the five delay conditions, which cover various environmental and manufacturing conditions. As a result, they are proved stable under each condition and improve the clock speed up to 17.3 % against the zero skew clock trees.

Abstract: The present invention coordinates the execution of commands, received in response to a continuous system clock, with the receipt of data in response to a burst clock. Command capture logic receives command information in response to the system clock. A storage element is responsive to the command capture logic for storing certain command information such as write commands. A two stage pipeline receives the command information from the storage element in response to the burst clock and outputs the command information in response to the system clock. Methods of operating the apparatus are also disclosed.

Abstract: Disclosed herein are circuits in which a plurality of clock signals are generated by corresponding clock generators from one or more common clock references. The clock generators accept control values that specify the phases of the individual clocks. The actual phase of each clock signal potentially varies during operation, and the phases of the various clock signal are generally independent of each other. To detect or measure phase relationships, the disclosed circuits evaluate or compare the control values using arithmetic logic.

Abstract: Causal consistency stipulates that causally dependent writes to data items should be executed in causal order. Traditionally this has been done by causally ordered message delivery using vector clocks. In a vector clock of size N, each element of the vector corresponds to each of the N hosts in the system and hence the message overhead is Θ(N). In a mobile environment the number of hosts can not be fixed because hosts join and leave the system dynamically. Hence traditional vector clocks are not suitable in a mobile environment. Consistency of a system consisting of M data items can be maintained using a vector in which each element corresponds to each data item. We propose a mechanism for maintaining causal consistency whose message overhead is Θ(M). Such a model will be advantageous in a mobile environment, because the message overhead is independent of the number of hosts. Further in applications such as collaboration the number of data items is small. Also, the delivery of a message is never inhibited due to causally overwritten messages.

Abstract: We introduce a clock schedule algorithm to obtain a clock schedule that achieves a shorter clock period and that can be realized by a light clock tree. A shorter clock period can be achieved by controlling the clock input timing of each register but the required wire length and power consumption of a clock tree tends to be large if clock input timings are determined without considering the locations of registers. To overcome the drawback, our algorithm constructs a cluster that consists of registers with the same clock input timing located in a close area. In our algorithm, first registers are partitioned into clusters by their locations, and clusters are modified to improve the clock period while maintaining the radius of each cluster small. In our experiments for an industrial data of 888 registers, the clock period achieved is 27% shorter than that achieved by a zero-skew clock tree, and 1% longer than the theoretical minimum. The computational time is about 24.9 seconds and the wire length and power consumption of the clock tree is comparable to those of a zero skew tree.

Abstract: The present invention has application to final balancing of an initial balanced clock tree. In one aspect of the invention, a minimum set of clock buffer delays is generated to reduce clock skew to within a selected skew limit for each level of a balanced clock tree. In one embodiment, the difference between the optimum delay and the clock buffer delay selected from the minimum set of clock buffer delays for each clock buffer in the balanced clock tree is less than or equal to the selected skew limit. In one such embodiment, a method of balancing a clock tree includes the steps of receiving as input a minimum buffer delay, a maximum level skew limit, and a selected skew limit; generating a minimum set of clock buffer delays for replacing at least one clock buffer in the balanced clock tree with a clock buffer delay selected from the minimum set of clock buffer delays such that the difference between the optimum delay and the clock buffer delay is less than or equal to the selected skew limit; and generating as output the minimum set of clock buffer delays.

Abstract: An N-clock system, for use for example in a ranging receiver using a Kalman filter. The clock system uses N clocks (to save power by using some clocks that consume less power) with a schedule for switching from one clock to another (so that only one clock is on at any instant of time). It uses an N-clock model that, in case of an application using clock 1 for time interval Δt1, clock 2 for time interval Δt2, . . . , and clock N for time interval ΔtN, provides a state update equation for updating the N-clock system state (the state components being typically time and fractional frequency). The state update equation results from propagating the state of the assembly of N clocks (providing a single output, i.e. acting as a single clock) forward from interval to interval until the entire interval of Δt1+Δt2+ . . . +ΔtN is covered.

Abstract: A model that allows asynchronous communication between agents in a timed decentralized discrete-event system is presented. Two needs for timing information are addressed: timing relationships between events and the maintenance of clocks for generating timestamps on messages sent between decentralized agents. An existing model of a timed automaton, called an event-recording automaton, is combined with a popular timing framework for determining the causality of messages in distributed systems, called vector clocks.

Abstract: A method and apparatus is provided for ensuring the integrity of data being transferred between two clock domains. Data is transferred on every clock signal from a faster clock domain to a slower clock domain. Data is collected by the data capture unit in two or more banks of registers for transfer to the second clock domain. The data collected has a first data size and is stacked with additional data of the first data size to generate data having a second data size. When two banks of registers are used, one bank of registers is being filled while the other bank of registers is passing data to the second clock domain. These two banks of registers provide two data paths to the synchronization logic for the second clock domain. This is especially advantageous when the limit of available bandwidth has been reached by one of the clock domains.

Abstract: Plausible Clocks do not characterize causality [6] but, under appropriate circumstances, their accuracy is close to vector clocks. This paper explores the effects that several factors have on the performance of these clocks.